Page Buffer Latch Update Mechanism for Program Verify Performance
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Solution Overview
Problem
Current page buffer systems in storage devices face inefficiencies in program verify operational performance, particularly in updating and managing program verification results across multiple program loops, which affects data storage and retrieval efficiency.
Innovation Solution
A page buffer system incorporating data latches, sensing latches, and a bit line voltage controller to store and update program verification results across program loops, enabling efficient data storage and retrieval by managing bit line voltages based on verification results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If program verification results are stored in a single latch structure, then the device complexity is reduced, but the program verify operational performance deteriorates due to inefficient updating and managing across multiple program loops
Solution Approach 1:
The patent divides the latch structure into multiple specialized latches (data latch, sensing latch, and bit line voltage controller) to handle different aspects of program verification results separately. This segmentation allows each latch to be optimized for its specific function, improving overall program verify operational performance while managing complexity through functional specialization.
2Productivity
If multiple latches are used to store verification results, then the data management efficiency improves, but the device complexity increases
Solution Approach 1:
The patent designs the multi-latch structure with universal update mechanisms where the bit line voltage controller can update verification results across all latches systematically. Each latch serves multiple purposes: storing current verification results, maintaining historical data, and participating in coordinated updates, thereby achieving efficient data management while controlling complexity through standardized multi-functional design.
3Productivity
If verification results are updated frequently across loops, then the operational performance improves, but the time consumption increases
Solution Approach 1:
The patent implements preliminary action by preparing and storing program verification results in dedicated latches during program operations, so that verification data is already organized and ready for rapid retrieval and updating. The bit line voltage controller is pre-configured to efficiently update latches during program operations, reducing the time penalty of frequent updates by having the update mechanism ready in advance.
Data Source
AI summary
An electronic device is provided. A page buffer includes at least one data latch, a sensing latch, and a bit line voltage controller. At least one data latch stores a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell. The sensing latch stores a program verification result of a current program loop among the plurality of program loops. The bit line voltage controller updates the program verification result of the previous program loop which is stored in the at least one data latch to the sensing latch during a program operation of a next program loop of the current program loop among the plurality of program loops.