Multi-Stage Page Buffer Layout for Compact 3D Non-Volatile Memory

The page buffer circuit is divided into multiple stages, with each stage handling a subset of bit lines. This segmentation allows the total area to be distributed across multiple smaller units rather than requiring one large buffer, thereby reducing the area occupied by any single page buffer while maintaining overall functionality and read reliability.

The patent transitions from a conventional two-dimensional layout to a three-dimensional stacked architecture where memory cell arrays are vertically stacked above the page buffer circuit. This vertical stacking enables the page buffer to serve multiple memory layers simultaneously, reducing the area required for the page buffer while maintaining access to all memory cells across stacked layers.

The patent implements a three-dimensional stacked memory architecture where multiple memory cell arrays are vertically stacked above the page buffer circuit. This vertical stacking enables increased memory capacity by adding more word lines in the vertical dimension rather than expanding horizontally, thereby increasing capacity while reducing the planar area occupied by the memory cell array.

The page buffer circuit is designed to universally serve multiple stacked memory cell arrays simultaneously. A single page buffer can access and operate on memory cells from different stacked layers, making the page buffer multi-functional across multiple memory arrays. This reduces the need for separate page buffers for each memory layer, thereby reducing total area while maintaining increased capacity through stacking.