Page Buffer Circuit Layout for NAND Flash Memory
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Solution Overview
Problem
NAND flash memory devices face challenges in balancing high write and read speeds with data retention, as they either lose data during power interruptions (volatile) or have low speeds (nonvolatile).
Innovation Solution
A memory device architecture is proposed, featuring a page buffer circuit with multiple page buffers and a cache circuit, where page buffers are divided into regions and disposed on both sides of the cache circuit, with separate page lines connecting each buffer to corresponding caches, optimizing data transfer and reducing wiring area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If page buffers are disposed at one side of the cache circuit, then the wiring layout is simple, but the wiring area is large and data transfer speed is reduced
Solution Approach 1:
The page buffer circuit is divided into first and second page buffer groups disposed at opposite sides of the cache circuit. This segmentation allows page lines to be distributed on both sides of the cache circuit, reducing the wiring area while maintaining short connection lengths for high-speed data transfer.
Solution Approach 2:
The page buffers are arranged in a two-dimensional layout around the cache circuit (both sides), rather than linearly on one side. This spatial redistribution reduces the overall wiring area while keeping individual page line lengths short, improving data transfer speed.
2Speed
If page buffers are disposed at both sides of the cache circuit, then the wiring area is reduced and data transfer speed is enhanced, but the circuit layout complexity increases
Solution Approach 1:
The page buffer circuit is segmented into two groups (first and second page buffer groups) positioned at opposite sides of the cache circuit. Each group connects to corresponding caches through dedicated page lines, simplifying the routing logic while achieving compact layout and high-speed transfer.
3Reliability
If separate page lines are used for each page buffer to corresponding caches, then data transfer reliability is improved, but the number of wiring lines increases
Solution Approach 1:
The page buffer circuit is divided into first and second page buffer groups, with each group having dedicated page lines connecting to corresponding cache groups. This segmentation ensures reliable data transfer through dedicated pathways while optimizing the total number of wiring lines by balanced distribution.
Data Source
AI summary
A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein the page buffer circuit is divided into a plurality of page buffer regions and is laid out at both sides of the cache circuit in the first direction.