Page Buffer Layout for Compact Non-Volatile Memory Read Reliability
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Solution Overview
Problem
The challenge in non-volatile memory devices is the increasing demand for reduced size and improved read reliability, particularly in the page buffer circuit, which occupies a significant area in the peripheral circuit.
Innovation Solution
A non-volatile memory device with a memory cell array and a multi-stage page buffer circuit, where the page buffer is positioned vertically below the memory cell array, featuring high and low voltage regions with specific widths and arrangements to optimize space utilization and enhance read reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the page buffer circuit is arranged horizontally next to the memory cell array, then the circuit layout is simple, but the device occupies a large area
Solution Approach 1:
The patent transitions from a horizontal arrangement to a vertical arrangement of the page buffer circuit below the memory cell array. This dimensional change in layout significantly reduces the occupied area while maintaining circuit functionality, directly resolving the area versus layout complexity contradiction.
2Area of stationary object
If the page buffer circuit size is reduced, then the device area decreases, but the read reliability deteriorates
Solution Approach 1:
The patent divides the page buffer circuit into distinct high voltage regions and low voltage regions with different widths. The high voltage region has a greater width than the low voltage region, optimizing the local dimensions of each functional area. This local quality differentiation maintains read reliability while reducing the overall circuit area.
Solution Approach 2:
The patent changes the width parameter of different regions within the page buffer circuit. Specifically, the high voltage region is designed with a greater width than the low voltage region, and these width ratios are optimized to maintain reliable read operations while minimizing the total area occupied by the page buffer circuit.
3Reliability
If the high voltage region width is increased, then the read reliability improves, but the page buffer circuit area increases
Solution Approach 1:
The patent optimizes the width parameter of the high voltage region to achieve the minimum necessary dimension for reliable read operations. By carefully controlling this parameter and differentiating it from the low voltage region width, the patent maintains read reliability while preventing excessive area expansion.
Solution Approach 2:
The patent applies different width characteristics to different functional regions within the page buffer circuit. The high voltage region is given a greater width than the low voltage region, but both are optimized to their minimum necessary dimensions, achieving local quality differentiation without overall area bloat.
Data Source
AI summary
Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.