Page Buffer Logic Circuit for Non-Volatile Encoding and Decoding
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Solution Overview
Problem
Volatile memory devices require continuous power to retain data, while non-volatile memory devices are slower, and there is a need for a page buffer that can operate efficiently with non-volatile memory devices, particularly for encoding and decoding operations.
Innovation Solution
A page buffer design incorporating a bit line connection circuit, latch circuits, and a logical operation circuit that performs operations using voltage levels of nodes as inputs, with a control circuit for verification, allowing for efficient logical operations and area optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory devices are used to eliminate continuous power supply requirement, then power retention capability is improved, but operation speed deteriorates
Solution Approach 1:
The page buffer is divided into multiple latch circuits (first latch circuit, second latch circuit, etc.) that can operate independently. This segmentation allows parallel processing of multiple data bits, compensating for the slower speed of non-volatile memory while maintaining data retention capabilities.
Solution Approach 2:
The latch circuits are designed with dynamic control signals (preset signal, clear signal, transfer signal) that enable flexible switching between different operational states. This dynamic operation allows the buffer to adapt to timing requirements and perform encoding/decoding operations efficiently despite the inherent slowness of non-volatile memory.
2Productivity
If multiple latch circuits are connected in parallel to increase buffering capacity, then data handling capability is improved, but circuit area increases
Solution Approach 1:
Multiple latch circuits share common control signals (preset signal, clear signal, transfer signal) and are integrated within a single page buffer structure. This merging approach allows parallel data handling while minimizing the area overhead that would result from completely independent latch circuits.
Solution Approach 2:
The latch circuits are designed to perform multiple functions: data buffering, encoding, and decoding operations. This multi-functionality allows a single page buffer structure to handle various data processing tasks, improving productivity without requiring separate dedicated circuits for each function.
3Adaptability or versatility
If logical operation circuit is added to enable encoding and decoding operations, then functionality is improved, but device complexity increases
Solution Approach 1:
The logical operation circuit is integrated within the page buffer structure, merging the buffering function with the encoding/decoding functionality. This combination allows the same circuit nodes (first node, second node) to serve multiple purposes: data storage and logical operations, thereby reducing overall device complexity.
Solution Approach 2:
The page buffer is designed to perform multiple operations: data buffering, logical operations (AND, OR, NOT), encoding, and decoding. This universal design allows a single circuit to replace what would traditionally require multiple separate components, improving versatility while managing complexity through shared circuitry.
Data Source
AI summary
A page buffer may include a bit line connection circuit configured to connect or disconnect a bit line and a first node, a plurality of latch circuits that is connected to the first node in common. The page buffer may further include, and logical operation circuit configured to perform a logical operation by using one or more of a voltage level of the first node and a voltage level of a second node as an input and to set the voltage level of the first node responsive to results of the operational operation.