Page Buffer Segmentation for Multi-bit Data Verification
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices, particularly flash memory, face challenges in efficiently programming and verifying multi-bit data due to limitations in controlling threshold voltages, leading to incomplete programming and verification of memory cells.
Innovation Solution
A page buffer system comprising a sense latch, data latch, and page buffer controller is introduced, which connects to the bit line and controls the bit line based on multi-bit data stored in the data latch, enabling precise programming and verification operations by outputting appropriate control signals during program and data verification operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data programming is implemented in flash memory, then data storage capacity is improved, but programming completeness and verification accuracy deteriorate due to threshold voltage control limitations
Solution Approach 1:
The page buffer is divided into separate functional components: a data latch for storing multi-bit data to be programmed, a sense latch for storing verification data, and a page buffer controller for coordinating operations. This segmentation allows each component to specialize in specific tasks, improving both programming completeness and verification accuracy while maintaining multi-bit storage capacity.
Solution Approach 2:
The sense latch acts as an intermediary between the bit line and the verification process. It temporarily stores sense data during verification operations, enabling accurate comparison with expected values from the data latch. This intermediary structure resolves the conflict between handling multi-bit data and maintaining verification precision.
2Device complexity
If a simple page buffer structure is used, then device complexity is reduced, but the ability to perform accurate multi-bit programming and verification deteriorates
Solution Approach 1:
The page buffer is segmented into distinct functional units: data latch for holding programming data, sense latch for holding verification data, and a controller for managing operations. This segmentation provides the necessary complexity for accurate multi-bit verification while keeping each individual component relatively simple and manageable.
Solution Approach 2:
The page buffer structure is designed to handle multiple functions: data input, data storage, verification, and control. By making the page buffer multi-functional, the design achieves accurate multi-bit programming and verification without requiring entirely separate dedicated circuits for each function, thus controlling overall device complexity.
3Speed
If threshold voltage control is simplified for faster programming, then programming speed is improved, but programming precision and data integrity deteriorate
Solution Approach 1:
The data latch stores the expected threshold voltage values or corresponding data patterns before the programming operation begins. This preliminary preparation allows the verification process to proceed quickly by simply comparing actual results against pre-stored expectations, maintaining both speed and precision without requiring complex real-time threshold voltage control.
Solution Approach 2:
The sense latch captures the actual threshold voltage results during or after programming, and the page buffer controller compares these results with the expected values stored in the data latch. This feedback mechanism ensures programming precision is maintained even with simplified programming control, as any deviations are detected and can trigger re-programming if necessary.
Data Source
AI summary
A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.