Memory Page Buffer Sensing With Multi-Latch Error Correction
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Solution Overview
Problem
Memory sub-systems experience non-trivial bit errors during initialization due to the use of default, non-optimized read parameters, which are not compensated by existing defect compensation features, leading to unreliable data retrieval.
Innovation Solution
Employing data redundancy and a sense operation with error correction by simultaneously selecting multiple latch elements to reinforce signal output on conducting lines, using a column select line signal generator to generate multiple select signals for a latch array, thereby compensating for errors and reducing the need for complex decoder circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If default read parameters are used during initialization, then the memory sub-system can perform basic data retrieval, but bit errors occur frequently and data reliability deteriorates
Solution Approach 1:
The patent performs preliminary defect identification and characterization during manufacturing before the memory device is shipped. Defect locations are mapped and stored in a defect compensation table, enabling the system to proactively avoid these locations during normal operation rather than reacting to errors after they occur
Solution Approach 2:
The patent creates redundant copies of data in alternative memory locations when defects are detected. Instead of relying on a single storage location, the system maintains multiple copies of critical data structures (such as the defect compensation table itself) in different physical locations to ensure availability even if one location becomes inaccessible
2Reliability
If multiple latch elements are selected simultaneously for error correction, then data integrity improves, but the complexity of the select signal generation increases
Solution Approach 1:
The patent combines multiple individual select signals into a single composite column select line signal. By merging the selection logic for multiple latch elements into one unified signal generation process, the system achieves error correction capability without proportionally increasing control complexity
Solution Approach 2:
The column select line signal generator is designed to perform multiple functions: it generates select signals for normal operation, generates select signals for error correction operations, and can dynamically adapt its behavior based on the operation mode. This multi-functionality reduces the need for separate dedicated circuits for different selection scenarios
3Reliability
If defect compensation features are enabled, then some errors can be corrected, but they do not compensate for errors during initialization with default parameters
Solution Approach 1:
The patent implements dynamic parameter adjustment where the memory sub-system automatically transitions from using default read parameters during initialization to using optimized read parameters after initialization. The system adapts its operating parameters based on the phase of operation, enabling error correction capabilities to be effective across different operational contexts
Solution Approach 2:
The memory sub-system performs self-initialization with error correction built into the initialization process itself. The defect compensation mechanisms are automatically activated and configured during initialization without requiring external intervention, and the system self-optimizes its parameters based on detected defects
Data Source
AI summary
Multiple copies of a stored data are sensed from a subset of memory cells of an array of memory cells into a plurality of latch elements in a page buffer coupled to the array of memory cells. Two or more latch elements are selected by enabling a respective select line of each of the two or more latch elements. An output data is determined based on a sensing of the conducting line driven by the two or more latch elements.