Page Buffer Latch Control for Multi-Level Memory Programming
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Solution Overview
Problem
Existing memory devices face inefficiencies in programming time and power utilization due to the inability to implement multi-level analog program convergence control, as current approaches can only apply data line bias voltages for a single programming level per program loop, leading to increased time and resource consumption.
Innovation Solution
Implementing multi-level analog program convergence control by using dynamic latch circuits with additional switches to selectively enable load paths for data line bias voltages, allowing simultaneous application of different bias voltages for multiple programming levels during the same program loop without requiring separate pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate program loops are used for each programming level, then programming accuracy is maintained, but programming time increases
Solution Approach 1:
The patent merges multiple separate program loops into a single unified program loop by enabling simultaneous application of different data line bias voltages for multiple programming levels. The dynamic latch circuits with additional switches allow each bit line to receive its appropriate bias voltage concurrently, eliminating the need for sequential processing while maintaining programming accuracy through controlled convergence.
Solution Approach 2:
The patent introduces dynamic control of data line bias voltages within a single program loop, allowing the bias voltages to be adjusted and converge to target values dynamically during the programming process. This dynamic approach enables multiple programming levels to be programmed simultaneously while maintaining precision through controlled voltage convergence rather than static sequential programming.
2Measurement precision
If separate program loops are used for each programming level, then programming precision is maintained, but power utilization increases
Solution Approach 1:
The patent combines multiple programming operations into a single program loop, reducing the total number of programming pulses and verify operations needed. By simultaneously programming multiple levels with coordinated bias voltages applied through dynamic latch circuits, the system reduces cumulative power consumption while maintaining programming precision through controlled convergence of the bias voltages to their target values.
3Adaptability or versatility
If additional switches are added to dynamic latch circuits, then multi-level analog program convergence control is enabled, but device complexity increases
Solution Approach 1:
The patent segments the control functionality by adding switches specifically to the load paths of dynamic latch circuits, allowing independent control of data line bias voltages for different programming levels. This segmentation enables multi-level analog program convergence control by selectively enabling or disabling specific bias voltage applications without requiring complete redesign of the entire latch circuit architecture.
Solution Approach 2:
The modified dynamic latch circuits with additional switches serve multiple functions: they can selectively apply different data line bias voltages for different programming levels, enable simultaneous programming of multiple levels, and maintain backward compatibility with existing memory cell structures. This multi-functionality achieves versatile multi-level control without proportionally increasing overall device complexity.
Data Source
AI summary
A memory device includes a memory array with a plurality of memory cells formed at respective intersections of a plurality of wordlines and a plurality of bit lines. The memory device further includes a page buffer circuit coupled to the memory array, the page buffer circuit having a plurality of dynamic latch circuits to store values representing respective data line bias voltages to be applied to the plurality of bit lines. Each of the plurality of dynamic latch circuits includes a storage element to store a value representing a respective data line bias voltage, a first switch and a second switch in a load path coupled to the storage element, wherein the value is loaded into the storage element via the load path with the first and second switches are activated, and a third switch in a decode path coupled the first switch in the load path, wherein the third switch is controlled by a shared decode load control signal.