Page Buffer Circuit with Multi-Time Sensing for Faster Reads

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Solution Overview

Problem

Non-volatile memories face challenges in performing quick and accurate read operations due to the need to discriminate between multiple data states in a single memory cell, requiring extensive time and multiple voltage checks.

Innovation Solution

A read operation method involving multiple sensing operations at different time points using varying read voltages applied to a sensing node, allowing for efficient discrimination of data states in a memory cell.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple voltage checks are performed to accurately discriminate data states in a memory cell, then measurement precision is improved, but loss of time increases

Engineering Contradiction:

Improvedata state discrimination accuracyVSAvoidread operation time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The read operation is divided into multiple sensing phases, each detecting voltage at different time points. The first sensing latch captures voltage at an early time point, while the second sensing latch captures voltage at a later time point. This segmentation allows parallel processing of multiple data state checks without sequential delays, resolving the contradiction between measurement precision and time loss.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first sensing latch performs preliminary sensing of the voltage level at an earlier time point during the evaluation period. This preliminary action prepares data that can be combined with the second sensing latch's results, enabling faster overall read operation while maintaining accurate discrimination of multiple data states through the combined information.

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If multiple sensing operations are performed at different time points, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improvevoltage level detection accuracyVSAvoidsensing circuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Two sensing latches are merged into a single page buffer circuit, with both latches sharing common circuit resources such as the sensing node and evaluation logic. This merging approach enables multiple sensing operations at different time points while avoiding the need for completely separate sensing circuits, thus improving measurement precision without proportionally increasing device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The page buffer circuit is designed with universal components that can perform multiple sensing functions. The same sensing node and evaluation circuitry are used by both the first and second sensing latches, allowing the circuit to detect voltage at multiple time points using a single multi-functional structure, thereby reducing overall device complexity while maintaining high measurement precision.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12462884B2Page buffer circuit and read operation method of memory

Publication Date: 2025.11.04 SK HYNIX INC

AI summary

Disclosed is a read operation method of a memory, and the read operation method may include evaluating a sensing node according to a voltage level of a bit line, sensing a voltage level of the sensing node after a first time elapses from a start of the evaluation, and sensing the voltage level of the sensing node after a second time longer than the first time elapses from the start of the evaluation.