Page Buffer Multi-Cache Scheme for Faster Memory Programming
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Solution Overview
Problem
Existing memory devices face challenges in reducing the size of peripheral circuits due to the increasing number of latches required for multi-level cells, which leads to performance issues in sequential program operations and data loading windows.
Innovation Solution
A multi-cache data loading scheme is implemented in the page buffer, reusing latches for both storing and caching data, reducing the number of latches needed and eliminating data loading windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of latches is increased to support multi-level cells, then the storage capacity is improved, but the peripheral circuit size increases
Solution Approach 1:
The patent applies multi-functionality by enabling latches to serve dual purposes: storing current data page information and caching next data page information. Specifically, latches in the page buffer circuit are configured to time-multiplex between holding current data and preparing next data, eliminating the need for separate dedicated storage resources and thereby reducing peripheral circuit size while maintaining support for multi-level cells
Solution Approach 2:
The patent implements preliminary action by having latches prepare and cache the next data page in advance during the programming of the current data page. This allows the system to overlap data preparation with data programming operations, reducing the need for additional latches and minimizing circuit complexity while supporting higher storage capacities
2Productivity
If more latches are used for multi-level cell programming, then the programming speed is improved, but the circuit size increases
Solution Approach 1:
The patent merges the functions of current data storage and next data caching into a single latch resource by using time-multiplexing. The same latch that stores current data page information is subsequently used to cache next data page information after the current programming operation completes, thereby achieving high programming speed without proportionally increasing circuit size
3Productivity
If data loading windows are eliminated, then the sequential program performance is improved, but the latch management complexity increases
Solution Approach 1:
The patent ensures continuity of useful action by maintaining overlapping operations where the page buffer circuit continuously prepares next data pages during the programming of current data pages. This eliminates data loading windows (idle periods) and maintains continuous productive operation, improving sequential program performance through systematic latch management
Data Source
AI summary
A memory device includes an array of memory cells columns and rows, word lines respectively coupled to rows of the memory cells, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit and word lines and including page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit configured to, in programming a select row based on a current data page, sequentially store each of N bits of the current data page and each of the N bits of a next data page, N−1 data storage units each configured to, in programming the select row based on the current data page, store a respective one of the N bits of the current data page and a respective one of the N bits of the next data page in a time division manner, and a multipurpose storage unit configured to, in programming the select row based on the current data page, store at least one of the N bits of the current data page.