Page Buffer Circuit Parasitic Capacitance for Sensing Accuracy
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Solution Overview
Problem
The size of memory devices is limited by the size of the actual sensing capacitor in page buffer circuits, which requires a large area for high capacitance, making it challenging to achieve both small size and high capacitance.
Innovation Solution
The use of parasitic capacitors formed between data bus sections and inner conductive lines in page buffers, without actual capacitors or extra metal routing, allows for large and stable capacitance without occupying additional space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If actual sensing capacitors are used in page buffer circuits to provide large capacitance, then sensing accuracy is improved, but device area increases
Solution Approach 1:
The patent converts parasitic capacitance, which is normally considered a harmful or unwanted effect in circuit design, into a beneficial sensing capacitor. By utilizing the inherent parasitic capacitance formed between the data bus section and inner conductive lines, the circuit achieves large sensing capacitance without requiring additional capacitor structures, thus improving sensing accuracy while maintaining compact device area.
Solution Approach 2:
The data bus section serves dual functions: it acts as both a signal transmission conductor and a sensing capacitor. The inner conductive lines, which are necessary for circuit operation, automatically form the parasitic capacitance structure needed for sensing. This self-service approach eliminates the need for separate capacitor components and their associated routing.
2Stability of the object's composition
If actual sensing capacitors with large capacitance are implemented, then sensing stability is improved, but device complexity increases
Solution Approach 1:
The data bus section is designed to perform multiple functions simultaneously: it serves as the signal transmission pathway and also functions as the sensing capacitor. The inner conductive lines, which are essential for circuit operation, automatically provide the capacitance structure. This multi-functionality reduces overall circuit complexity while maintaining stable sensing performance.
3Measurement precision
If large actual capacitors are used to provide sufficient sensing capacitance, then sensing performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent transforms parasitic capacitance, typically viewed as an unwanted side effect, into a useful sensing resource. By doing so, it eliminates the need for additional capacitor components and their associated manufacturing processes, reducing fabrication complexity and cost while achieving the required sensing performance.
Solution Approach 2:
The existing conductive structures in the circuit automatically provide the capacitance function needed for sensing. No additional manufacturing steps or specialized components are required, as the necessary capacitance emerges naturally from the circuit's own conductive elements during normal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of device area, minimizes capacitor variation, reduces power consumption, and improves sensing accuracy by providing a larger sensing capacitance without the need for large actual capacitors.
Implementation Method 1
Each DBUS section can be configured to form a parasitic capacitor with at least one inner conductive line in the page buffer for the data sensing
Data Source
AI summary
Systems, methods, circuits, and apparatus for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, a page buffer circuit including a plurality of page buffers, and a cache data latch (CDL) circuit including a plurality of caches coupled to the plurality of page buffers through a plurality of data bus sections. The plurality of data bus sections are configured to be conductively connected together as a data bus for data transfer. Each data bus section corresponds to a page buffer in the page buffer circuit and is configured to conductively separate from at least one adjacent data bus section for data sensing in the memory cell array.