Page Buffer Precharge Scheme for Faster Program Verification
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Solution Overview
Problem
The time required to change the level of a verification voltage applied to a word line during program verification operations in memory devices is significant, occupying a large proportion of the total program operation time.
Innovation Solution
A memory device with a page buffer circuit that maintains the level of a verification voltage applied to a word line by precharging sensing nodes to different levels for different program states and using a boost voltage to increase the voltage level of sensing nodes during verification, allowing simultaneous verification of multiple program states without changing the verification voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the verification voltage level is changed to verify different program states, then different program states can be verified, but the time required for verification operations increases significantly
Solution Approach 1:
The patent changes the precharge voltage level parameter of the sensing node instead of changing the verification voltage applied to the word line. By adjusting the precharge voltage to different levels (first level for first program state, second level for second program state), the system can verify different program states while keeping the verification voltage constant, thus reducing verification time
Solution Approach 2:
The patent applies preliminary action by precharging the sensing node to appropriate voltage levels before verification operations. The precharge circuit prepares the sensing node in advance with different voltage levels depending on which program state is being verified, enabling faster verification without requiring voltage level changes during the actual verification process
2Loss of time
If the verification voltage level is maintained constant, then verification time is reduced, but the ability to verify different program states is limited
Solution Approach 1:
The patent compensates for the constant verification voltage by changing other parameters - specifically the precharge voltage level of the sensing node. This alternative parameter change enables the system to differentiate between different program states (first program state vs. second program state) without needing to change the verification voltage, thus maintaining fast verification speeds
Solution Approach 2:
The sensing node acts as an intermediary between the verification voltage and the readout circuitry. By manipulating the precharge voltage of this intermediary element rather than the verification voltage itself, the system can encode different verification conditions while maintaining a constant verification voltage level
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for verification operations by enabling the simultaneous verification of multiple program states while maintaining a constant verification voltage level, thereby enhancing program speed.
Implementation Method 1
precharge a first sensing node of the first page buffer connected to the first memory cell to a first level in a first precharge period during verification of a first program state of the first memory cell, and precharge a second sensing node of the second page buffer connected to the second memory cell to a second level in a second precharge period during verification of a second program state of the second memory cell
Implementation Method 2
a boost voltage controller configured to apply to boost nodes of page buffers of memory cells selected for verification of the second program state, a boost voltage during verification of the second program state to increase the voltage level of sensing nodes of the page buffers from the first level to a second level higher than the first level
Implementation Method 3
a row decoder configured to apply a verify voltage to a word line commonly connected to the first memory cell and the second memory cell during the first precharge period and the second precharge period
Data Source
AI summary
A memory device includes a memory cell array, and a page buffer circuit including a plurality of page buffers selectively connected to memory cells via a plurality of bit lines, each of the plurality of page buffers including a sensing node. The sensing nodes may be charged to different levels during verification of programming states of the memory cells. For example, a first sensing node of a first page buffer connected to a first memory cell targeted for programming to a first program state from among the plurality of page buffers is precharged to a first level in a first precharge period during verification of the first program state. A second sensing node of a second page buffer connected to a second memory cell targeted for programming to a second program state charged to a second level during verification of the second program state, wherein the second level is different from the first level.