Page Buffer Precharge Voltage Control for Memory Devices
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Solution Overview
Problem
Memory devices face challenges in reducing current consumption and variations in bit line currents or voltages during precharging, which affects the reliability of program verify operations.
Innovation Solution
A memory device with a page buffer that applies a first precharge voltage to bit lines for program data and a second precharge voltage, lower than the first, for erase data, using separate precharge circuits and paths to manage current consumption and voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single precharge voltage is applied to bit lines, then the circuit structure is simple, but current consumption increases and voltage variations occur during precharging
Solution Approach 1:
The precharge circuit is segmented into multiple independent precharge circuits (first precharge circuit and second precharge circuit), each capable of providing different precharge voltages. This segmentation allows selective activation of precharge paths based on data type, reducing overall current consumption while maintaining circuit functionality.
Solution Approach 2:
The precharge voltage is made dynamic by selectively activating different precharge circuits based on the data type (program data or erase data). The circuit transitions from a static single-voltage approach to a dynamic multi-voltage approach, optimizing current consumption for different operational states.
2Device complexity
If a single precharge voltage is applied to bit lines, then the circuit structure is simple, but voltage variations occur during precharging
Solution Approach 1:
Different precharge voltages are applied to different bit lines based on their specific operational requirements. Program data bit lines receive a first precharge voltage optimized for program verify operations, while erase data bit lines receive a second precharge voltage. This local optimization reduces voltage variations and improves reliability without requiring complete circuit redesign.
3Use of energy by moving object
If different precharge voltages are applied to bit lines, then current consumption is reduced and voltage variations are minimized, but the precharge circuit structure becomes more complex
Solution Approach 1:
Multiple precharge circuits are designed with identical or similar structural configurations, each capable of providing different precharge voltages. This multi-functionality approach allows the system to handle different data types with optimized voltages while maintaining structural consistency, making the complexity manageable and scalable.
4Reliability
If different precharge voltages are applied to bit lines, then program verify operation reliability is improved, but the precharge circuit structure becomes more complex
Solution Approach 1:
Different precharge voltages are applied to different bit lines based on their specific operational requirements. Program data bit lines receive a first precharge voltage optimized for program verify operations, while erase data bit lines receive a second precharge voltage. This local optimization reduces voltage variations and improves reliability without requiring complete circuit redesign.
Data Source
AI summary
Provided herein may be a memory device having a page buffer. The memory device may include a memory cell configured to store data, and a page buffer coupled to the memory cell through a bit line and configured to store data to be used in a program operation and to precharge the bit line to a first precharge voltage or a second precharge voltage lower than the first precharge voltage depending on the data during a program verify operation performed in the program operation.