Page Buffer Program Verify Optimization

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Solution Overview

Problem

Current semiconductor memory devices face inefficiencies in program operations due to the need for repeated verify operations across multiple program states, which prolong the overall programming time.

Innovation Solution

The implementation of a page buffer system that temporarily stores program data, controls node values based on memory cell states, and selectively latches verification data, allowing for efficient program verify operations by masking unnecessary data and optimizing bit line precharging and discharging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If repeated verify operations are performed across multiple program states, then programming reliability is improved, but programming time increases

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The page buffer pre-latches program data before the actual programming operation begins. This preliminary action allows the verification process to operate on pre-prepared data without waiting for sequential data retrieval, thereby reducing verification time while maintaining reliability across multiple program states

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The page buffer is divided into multiple data latch components, each handling specific program data. This segmentation allows parallel processing of different data portions during verification operations, reducing the overall time required while ensuring each segment undergoes necessary reliability checks

Inventive Principle:

Principle #1Segmentation

2Reliability

If all program data is processed during verify operations, then verification completeness is improved, but operation time increases

Engineering Contradiction:

Improveverification completenessVSAvoidoperation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The sub-latch component extracts and holds only the verification data that is currently being checked, separating it from the complete program data set. This extraction allows the verification operation to focus on specific data portions without the overhead of processing all program data, reducing operation time while maintaining verification completeness for the targeted data

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The page buffer performs verification on specific portions of data at each operation stage rather than all data simultaneously. This partial action approach allows multiple verification passes to occur in parallel or sequence without blocking, achieving complete verification across all data while reducing the time any single verification operation must run

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11842773B2Page buffer, semiconductor memory device with page buffer, and method of operating semiconductor memory device

Publication Date: 2023.12.12 SK HYNIX INC

AI summary

Provided herein is a page buffer, a semiconductor memory device with the page buffer, and a method of operating the semiconductor memory device. The page buffer includes a plurality of data latch components coupled to a sensing node, a bit line controller coupled between a bit line and the sensing node, the bit line controller configured to control a node value of the sensing node based on a program state of a memory cell that is coupled to the bit line during a program verify operation, and a sub-latch component configured to latch verification data based on the node value during the program verify operation, wherein each data latch component sets the node value to a first logic value when a program state that corresponds to program data has a threshold voltage distribution that is higher than that in a target program state during the program verify operation.