Page Buffer Circuit Sensing Latch Design for Memory Devices
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Solution Overview
Problem
Integrated circuit memory devices face challenges in reducing the size of page buffer circuits while maintaining large and stable capacitance for accurate sensing, as existing sensing capacitors require a large area.
Innovation Solution
The implementation of a page buffer circuit with a sensing latch circuit and a storage latch circuit, where the sensing latch circuit includes a sensing transistor with a gate terminal connected to a sensing node for sensing data through a bit line, and the storage latch circuit does not include a sensing transistor, minimizing the number of sensing transistors to reduce capacitance variance and stabilize the capacitance at the sensing node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large sensing capacitor is used to sense data accurately, then sensing accuracy is improved, but device area increases
Solution Approach 1:
The patent merges the sensing capacitor function with the gate capacitor of the sensing transistor. The gate capacitor, which is inherently part of the transistor structure, serves dual purposes: as the gate control element and as the sensing capacitor. This eliminates the need for a separate large-area sensing capacitor while maintaining accurate sensing capability.
Solution Approach 2:
The gate capacitor of the sensing transistor performs multiple functions: it acts as both the gate control element for transistor operation and as the sensing capacitor for data detection. This multi-functionality reduces the total component count and device area while preserving sensing accuracy.
2Measurement precision
If multiple sensing transistors are used in the latch circuit, then sensing capability is improved, but capacitance variance increases
Solution Approach 1:
The patent extracts the sensing transistor from the latch circuit, leaving only storage latches. The sensing transistor operates independently with its gate capacitor serving as the sensing capacitor, disconnected from the latch feedback paths. This eliminates the capacitance variance introduced by latch transistors while maintaining sensing capability.
Solution Approach 2:
The patent segments the circuit into distinct functional blocks: a sensing portion with the sensing transistor and its gate capacitor, and a storage portion with separate latches. This segmentation isolates the sensing function from the storage function, preventing capacitance interaction and variance while maintaining both capabilities.
3Reliability
If sensing transistor gate terminal is connected to latch circuits, then data storage is improved, but capacitance variance increases
Solution Approach 1:
The patent extracts the sensing transistor gate terminal connection from the latch circuits. The gate terminal is connected only to the sensing node, not to the latch feedback paths. This separation eliminates the capacitance variance introduced by latch transistors while maintaining data storage capability through dedicated storage latches.
Solution Approach 2:
The patent segments the circuit into distinct functional blocks: a sensing portion with the sensing transistor and its gate capacitor, and a storage portion with separate latches. This segmentation isolates the sensing function from the storage function, preventing capacitance interaction and variance while maintaining both capabilities.
Data Source
AI summary
Systems, methods, circuits, and apparatus including computer-readable mediums for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, memory cell lines connecting respective lines of memory cells, and a page buffer circuit including page buffers coupled to the memory cell lines. Each page buffer includes a sensing latch circuit and a storage latch circuit. The sensing latch circuit includes a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to a first terminal of the sensing transistor. The storage latch circuit includes at least one storage latch unit having third and fourth nodes coupled to the sensing node and a gate terminal of the sensing transistor. A second terminal of the sensing transistor is coupled to a ground.