Page Buffer Circuit Sensing Node Voltage Stabilization
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Solution Overview
Problem
Nonvolatile memory devices, such as NAND flash, require an erase operation to overwrite data, but existing erase-verification methods are inefficient and prone to errors due to voltage level fluctuations during multi-string-based-erase-verification operations.
Innovation Solution
A page buffer circuit with an intermediate circuit, data storage circuit, and enhancive circuit is introduced, which applies operational voltages to a sensing node to pre-charge and maintain a stable voltage level, preventing voltage drops and enhancing capacitance during erase-verification operations, thereby improving accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-string-based-erase-verification operation is performed, then verification speed is improved, but voltage level stability deteriorates causing measurement errors
Solution Approach 1:
A sensing node is introduced as an intermediary between the bit line and the page buffer circuit. The sensing node captures and holds the voltage level corresponding to the memory cell status, isolating the detection process from voltage fluctuations on the bit line during multi-string operations, thereby maintaining measurement precision while enabling high-speed verification
Solution Approach 2:
The sensing node is pre-charged to a reference voltage level before the erase-verification operation begins. This preliminary action establishes a stable baseline that allows accurate detection of voltage changes caused by memory cell status, even when multiple strings are operated simultaneously with varying current demands
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the speed and accuracy of erase-verification operations by maintaining a stable voltage level, reducing errors and ensuring proper determination of memory cell statuses within the nonvolatile memory device.
Implementation Method 1
The enhancive circuit may be coupled to the sensing node and may be configured to increase a capacitance of the sensing node in an enhancive interval during a selected operation
Implementation Method 2
The intermediate circuit may be configured to apply a first operational voltage to a sensing node to pre-charge the sensing node and may be configured to apply a voltage having a voltage level, corresponding to a status of a plurality of strings, to the sensing node during a multi-string-based-erase-verification operation
Data Source
AI summary
A page buffer circuit includes an intermediate circuit, a data storage circuit and an enhancive circuit. The intermediate circuit is coupled to a bit line coupled to a memory region and configured to apply a voltage having a voltage level, corresponding to a status of the memory region, to a sensing node. The data storage circuit is configured to store, therein, a value that corresponds to the status of the memory region in response to the voltage level. The enhancive circuit is coupled to the sensing node and configured to increase a capacitance of the sensing node in an enhancive interval during a selected operation.