Page Buffer Circuit with Serial Sensing Nodes
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Solution Overview
Problem
The increasing demand for higher integration and larger capacity in memory devices leads to a complex layout of wires connected to semiconductor devices in page buffers, making it challenging to maintain sensing reliability.
Innovation Solution
A page buffer circuit is designed with page buffer units and cache units arranged in a specific configuration, where sensing nodes are connected in series through pass transistors, reducing the need for separate data transmission lines and simplifying the layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor devices in the page buffer is reduced to increase integration, then the degree of integration is improved, but the layout of wires connected to semiconductor devices becomes complicated
Solution Approach 1:
The page buffer circuit is divided into multiple page buffer units (first set and second set) with cache units arranged between them. Each page buffer unit has its own sensing node and pass transistor, allowing modular wiring that reduces overall layout complexity while maintaining high integration.
Solution Approach 2:
Sensing nodes from multiple page buffer units are electrically connected to one another through serial connections of pass transistors during data transmission period. This merging approach allows shared sensing infrastructure, reducing the number of separate wires needed and simplifying the layout.
2Area of stationary object
If the page buffer size is reduced to increase integration, then the area occupied by the page buffer is reduced, but sensing reliability may deteriorate
Solution Approach 1:
The page buffer is segmented into multiple units with dedicated sensing nodes, allowing each unit to maintain proper sensing characteristics while the overall area is reduced through shared infrastructure. The segmentation enables localized sensing that preserves reliability despite area reduction.
Solution Approach 2:
The pass transistors serve dual functions: they act as switches during data transmission period and as connection elements during sensing period. This multi-functionality reduces the need for separate sensing infrastructure, maintaining sensing reliability while reducing overall area.
3Reliability
If separate data transmission lines are used for each page buffer unit, then data transmission is reliable, but the layout becomes more complex
Solution Approach 1:
Instead of providing separate data transmission lines for each page buffer unit, the patent merges the transmission path by connecting sensing nodes through serial pass transistors. This shared transmission path maintains reliability through controlled switching while significantly reducing layout complexity.
Solution Approach 2:
The pass transistors are selectively turned on during data transmission period to enable dynamic connection between sensing nodes. This dynamic switching allows the same physical infrastructure to serve multiple units without interference, maintaining reliability while simplifying the static layout.
Data Source
AI summary
A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.