Page Buffer Stagger Control for Lower-Current Memory Layouts
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Solution Overview
Problem
The increasing complexity of layout design for signal lines in semiconductor memory due to reduced transistor size complicates the arrangement and increases difficulty in reducing peak current during memory operations.
Innovation Solution
The implementation of a stagger control mechanism for semiconductor memory systems, where operation voltages are sequentially applied to groups of page buffers through stagger control lines, reducing the number of signal and stagger control lines required, thereby simplifying the layout design and reducing peak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to improve integration density, then memory capacity increases, but routing layout complexity increases
Solution Approach 1:
The page buffer is divided into multiple groups (first page buffer group and second page buffer group), each controlled by separate stagger control lines. This segmentation allows independent control of different page buffer groups, reducing the complexity of routing layouts by organizing controls in a modular fashion rather than requiring a single complex control structure for all page buffers.
2Device complexity
If all page buffers are controlled simultaneously, then control logic is simple, but peak current increases
Solution Approach 1:
The patent implements staggered control where the control logic circuit sequentially activates different page buffer groups at different time periods. The first page buffer group is controlled in a first time period, and the second page buffer group is controlled in a second time period. This periodic staggered activation prevents all page buffers from being activated simultaneously, thereby reducing peak current while maintaining manageable control logic complexity through timing sequencing.
3Power
If more control lines are added for stagger control, then peak current is reduced, but routing complexity increases
Solution Approach 1:
Multiple control functions are merged into the control logic circuit, which integrates the staggering control mechanism with existing control signals. The control logic circuit generates stagger control signals based on combined control requirements, reducing the need for separate independent control lines for each page buffer group. This merging approach reduces routing complexity while still achieving peak current reduction through coordinated control.
Data Source
AI summary
The application provides a memory includes a memory array and a peripheral circuit coupled to the memory array, wherein the peripheral circuit includes a control logic circuit and a page buffer. The page buffer includes a first page buffer and a second page buffer, the control logic circuit is coupled to the first page buffer through a first stagger control line, and is coupled to the second page buffer through a second stagger control line. The control logic circuit is configured to: apply an operation voltage to the page buffer through a signal line; and during the application of the operation voltage to the page buffer, apply a control voltage to the first page buffer through the first stagger control line in a first stage, and apply a control voltage to the second page buffer through the second stagger control line in a second stage.