Page Buffer Switching for Bit Line Interference in Memory Devices
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Solution Overview
Problem
As the integration of memory devices increases, interference between bit lines during read or verify operations deteriorates the reliability of memory devices due to narrowed intervals, leading to false sensing of programmed cells as erased cells.
Innovation Solution
The memory device incorporates a page buffer system with switches that adjust the turn-on levels of bit lines to prevent voltage drops, using a common sensing node and latch configuration to accurately sense threshold voltages, thereby reducing interference and enhancing sensing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory device is increased, then storage capacity is improved, but interference between bit lines increases causing reliability deterioration
Solution Approach 1:
The patent adjusts the turn-on level of the first switch by changing the voltage level of the sensing signal. This parameter change allows the switch to selectively conduct based on the sensed voltage level, preventing interference between adjacent bit lines while maintaining high integration density. By dynamically adjusting the switch's turn-on threshold, the system compensates for capacitive coupling effects between closely spaced bit lines.
2Area of moving object
If the interval between bit lines is narrowed to increase integration, then storage density is improved, but interference between bit lines during read operations increases
Solution Approach 1:
The patent introduces a sensing node as an intermediary between the bit line and the latch. The sensing node temporarily stores the voltage level from the bit line before transferring it to the latch. This intermediary structure allows the system to read the voltage level without directly coupling adjacent bit lines, thereby reducing interference while maintaining narrow spacing for high density.
Solution Approach 2:
The patent performs preliminary sensing of the bit line voltage level before transferring it to the latch. By first sensing the voltage level at the sensing node and only then activating the latch based on this preliminary information, the system prevents premature or incorrect latch activation that could cause interference between adjacent bit lines during read operations.
3Speed
If the voltage of bit line is transferred directly to latch, then sensing speed is improved, but voltage drops sharply causing false sensing errors
Solution Approach 1:
The patent performs preliminary sensing of the bit line voltage at the sensing node before transferring the signal to the latch. This preliminary action allows the system to prepare the latch for accurate reading by first establishing the correct voltage level at the sensing node, preventing sharp voltage drops and ensuring precise voltage-level-based sensing while maintaining fast operation.
Data Source
AI summary
Provided herein is a memory device and a method of operating the same. The memory device may include a string having a plurality of memory cells in which data is stored, and a page buffer coupled to the string through a bit line and configured to precharge the bit line, or sense voltage or current of the bit line. The page buffer may include a first switch configured to transfer the voltage of the bit line to a common sensing node in response to a page buffer sensing signal, a second switch configured to transfer a supply voltage to the common sensing node in response to a common sensing signal, and a third switch configured to couple the common sensing node to a latch in response to a sensing signal and adjust voltage of the common sensing node depending on a voltage level of the sensing signal.