Page Buffer Voltage Segmentation for Flash Programming Precision
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Solution Overview
Problem
Flash memory devices face issues with wide distribution of threshold voltages during programming, leading to narrow read margins and deteriorated performance due to difficulty in maintaining consistent programming and erasing operations.
Innovation Solution
Implementing two charge/discharge circuits in a page buffer to apply distinct bit line forcing voltages, higher than the programming voltage but lower than the programming-inhibit voltage, to control and refine the threshold voltage distribution of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single charge/discharge circuit is used to apply bit line voltages during programming, then the device complexity is reduced, but the threshold voltage distribution becomes wide leading to narrow read margins
Solution Approach 1:
The single charge/discharge circuit is segmented into two independent charge/discharge circuits. Each circuit independently controls a portion of the bit line, allowing separate voltage application with different forcing characteristics. This segmentation enables precise control over threshold voltage distribution by applying tailored voltages to different memory cell groups, thereby narrowing the overall threshold voltage distribution while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
Different regions of the bit line are assigned different voltage characteristics through the two charge/discharge circuits. The first circuit applies a first bit line forcing voltage to a first portion of the bit line, while the second circuit applies a second bit line forcing voltage to a second portion. This local quality approach ensures that each region receives optimized voltage control suited to its specific programming requirements, improving threshold voltage uniformity across the entire memory array.
2Productivity
If higher bit line forcing voltages are applied to speed up programming, then programming speed increases, but the threshold voltage distribution widens reducing read margins
Solution Approach 1:
The system dynamically adjusts voltage parameters by applying different bit line forcing voltages from two charge/discharge circuits. The first circuit applies a first bit line forcing voltage while the second circuit applies a second bit line forcing voltage, with both voltages being higher than the programming bit line voltage but lower than the programming-inhibit bit line voltage. This parameter differentiation allows optimization of programming speed while controlling threshold voltage distribution through tailored voltage selection for each circuit.
Solution Approach 2:
The two charge/discharge circuits enable dynamic voltage control during programming operations. By independently managing the voltage application timing and magnitude from each circuit, the system can adaptively adjust bit line voltages based on real-time programming progress and cell state. This dynamic control prevents excessive voltage application that would widen threshold distribution, while maintaining sufficiently high voltages to ensure fast programming when appropriate.
3Manufacturing precision
If consistent programming voltage is applied to all memory cells, then programming simplicity is maintained, but threshold voltage distribution widens due to process variations
Solution Approach 1:
The memory array is segmented into regions corresponding to the two charge/discharge circuits, allowing differentiated voltage control. The first charge/discharge circuit manages a first portion of the bit line with a first bit line forcing voltage, while the second circuit manages a second portion with a second bit line forcing voltage. This segmentation compensates for process variations by enabling localized voltage adjustment, improving threshold voltage consistency across the entire array while maintaining relatively simple circuit architecture through systematic division.
Solution Approach 2:
The two charge/discharge circuits enable feedback-based voltage control during programming. By monitoring programming progress and threshold voltage development, the control logic can adjust the operation of each circuit to maintain optimal voltage levels. This feedback mechanism ensures consistent threshold voltage programming across memory cells despite process variations, while the feedback loop itself adds minimal complexity compared to the benefits gained in voltage control precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach narrows the threshold voltage distribution, improving the stability and accuracy of programming operations by ensuring consistent programming across memory cells.
Implementation Method 1
The first charge/discharge circuit is configured to store first bit line forcing information and apply a first bit line forcing voltage to the bit line based on the first bit line forcing information
Implementation Method 2
The second charge/discharge circuit coupled to the bit line and configured to store a second bit line forcing information, and apply a second bit line forcing voltage, different from the first bit line forcing voltage, to the bit line based on the second bit line forcing information
Data Source
AI summary
A page buffer includes a first charge/discharge module and a second charge/discharge module. The first charge/discharge module includes a first charge/discharge circuit, and a first latch. The first latch is coupled to the first charge/discharge circuit and a first sense node of the page buffer. The second charge/discharge module includes a second charge/discharge circuit, a second latch coupled to the second charge/discharge circuit, and a second bit line voltage setting circuit. The second charge/discharge circuit and the second bit line voltage setting circuit are coupled to the first sense node.