Page Buffer Timing Control for Stable Multi-Plane Memory Operation
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Solution Overview
Problem
The simultaneous operation of multiple page buffer groups in memory devices leads to a significant load current, affecting the power supply quality and reducing the reliability and efficiency of program/read operations.
Innovation Solution
The memory device is designed with a control logic that staggered the performing time periods for page buffer groups, ensuring that the time periods of one group do not overlap with others, thereby managing the load current and improving power supply quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple page buffer groups operate simultaneously, then program/read operations can be performed in parallel improving productivity, but load current increases significantly affecting power supply quality and reliability
Solution Approach 1:
The page buffer circuit is divided into multiple independent page buffer groups (first, second, third, and fourth groups), each capable of independent operation. This segmentation allows the system to control which groups operate simultaneously, thereby managing load current while maintaining parallel processing capabilities for improved productivity.
2Productivity
If multiple page buffer groups operate simultaneously, then processing capacity increases, but abrupt changes in load current occur reducing reliability
Solution Approach 1:
The control logic implements periodic action by sequentially enabling different page buffer groups at different time periods. Instead of all groups operating simultaneously, they are activated in a staggered manner (first group in first time period, second group in second time period, etc.), which smooths out load current changes and improves power supply stability while still providing substantial parallel processing capacity.
Data Source
AI summary
Examples of the present disclosure provide a memory device and an operation method thereof, and a memory system. The memory device includes: a memory cell array including memory cells, wherein the memory cells are divided into memory planes; bit lines; page buffer circuits, wherein each of the page buffer circuits includes page buffer groups, and corresponds to one of the memory planes, and the page buffer circuit performs a buffer operation in response to a buffer operation command; and a control logic coupled to the page buffer groups and configured to: for each of the memory planes, provide the buffer operation command to the plurality of page buffer groups, and control performing time periods for the page buffer groups to perform the buffer operation such that some performing time periods among the plurality of performing time periods overlaps.