Page Buffer Timing Layout for Reliable Nonvolatile Memory Sensing
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Solution Overview
Problem
The reliability of data detected through a page buffer in nonvolatile memory devices is degraded due to the influence of the sensing node voltage of an adjacent page buffer.
Innovation Solution
A nonvolatile memory device is designed with a page buffer circuit and a page buffer controller, where the develop timing of sensing nodes in different page buffers is differentiated, and the page buffers are arranged such that one is closer to the through electrode region than the other, reducing coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple page buffers are arranged closely to increase integration density, then device area is reduced, but the reliability of data detection is degraded due to sensing node voltage coupling between adjacent page buffers
Solution Approach 1:
The sensing node development process is segmented into different time periods for adjacent page buffers. The page buffer controller develops sensing nodes in first page buffers during a first time period and in second page buffers during a second time period, separating the voltage transition events to prevent coupling interference while maintaining close physical arrangement
Solution Approach 2:
The page buffer controller performs preliminary actions by controlling the timing of sensing node development. Before adjacent page buffers can interfere with each other's voltage signals, the controller sequentially activates different groups of page buffers at different times, preventing the harmful coupling effect before it occurs
2Speed
If sensing nodes in adjacent page buffers develop simultaneously, then detection speed is improved, but voltage changes in one page buffer interfere with data detection in adjacent page buffers
Solution Approach 1:
The page buffer controller implements periodic action by dividing the sensing node development into different time periods. First page buffers are developed during a first time period while second page buffers are developed during a second time period, creating a sequential periodic pattern that eliminates voltage interference while maintaining efficient detection speed
3Device complexity
If all page buffers operate at the same timing, then device complexity is reduced, but the sensing node voltage of one page buffer affects adjacent page buffers causing detection errors
Solution Approach 1:
The page buffer controller implements dynamic control by adjusting the operation timing of different page buffers based on their spatial arrangement. Page buffers are divided into groups that operate at different times, creating a dynamic temporal pattern that adapts to the physical layout and prevents voltage coupling interference
Data Source
AI summary
A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.