Page Buffer Transistors with Asymmetric Stress for Memory Reliability
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Solution Overview
Problem
In vertical non-volatile memory devices with 3D memory cell arrays, transistors in the page buffer region experience threshold voltage variations due to mold stress during the formation process, leading to inconsistent performance and reliability issues.
Innovation Solution
The design incorporates a memory cell array region with vertically stacked memory cells and a page buffer region where first and second page buffers are arranged with different distances from the memory cell array, featuring transistors with distinct sizes and tensile stresses to minimize threshold voltage differences, and a manufacturing method that adjusts implant concentrations to compensate for these differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors in the page buffer region are formed with uniform design and processing constraints, then manufacturing simplicity is maintained, but threshold voltage variations occur due to mold stress leading to inconsistent performance
Solution Approach 1:
The patent applies different design constraints (transistor sizes) and processing constraints (tensile stresses, implant concentrations) to transistors based on their specific locations in the page buffer region. First page buffers closer to the memory cell array receive different treatment than second page buffers farther away, compensating for location-dependent mold stress effects and achieving uniform threshold voltages across all transistors.
2Reliability
If all page buffers are positioned at the same distance from the memory cell array, then layout simplicity is maintained, but threshold voltage variations due to mold stress cannot be compensated
Solution Approach 1:
The patent deliberately creates an asymmetric layout where first page buffers are positioned at a first distance from the memory cell array region and second page buffers are positioned at a second distance, greater than the first distance. This asymmetric arrangement allows differential application of tensile stress and implant concentration to compensate for mold stress variations across different locations in the page buffer region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces threshold voltage variations between transistors, enhancing the reliability and performance of the non-volatile memory device by optimizing transistor sizes and stress conditions based on their locations within the page buffer region.
Implementation Method 1
a first page buffer comprising a first transistor having a first tensile stress; and forming a second page buffer comprising a second transistor having a second tensile stress
Implementation Method 2
a first value of a manufacturing constraint for forming the first transistor is different from a second value for the same manufacturing constraint for forming the second transistor. The first and second values of the manufacturing constraint are selected to reduce a threshold voltage difference existing between the first and second transistors
Data Source
AI summary
A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.