Page Buffer Transistor Layout for Erase Stability
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Solution Overview
Problem
In semiconductor memory devices, the existing configuration of bit line select transistors and erase bias pass transistors being adjacent to each other leads to increased wiring line tracks and load, causing instability and inefficiency in erase operations due to shared wiring lines and drain regions.
Innovation Solution
The transistors are disposed in different regions, with bit line select transistors in one region and erase bias pass transistors in another, allowing for staggered active regions and shared drain regions, reducing the number of wiring lines and increasing the width and spacing between them to stabilize erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bit line select transistors and erase bias pass transistors are disposed adjacent to each other, then device area is reduced, but wiring line load and interference increase causing instability in erase operations
Solution Approach 1:
The patent divides the transistor arrangement into two separate regions: bit line select transistors are disposed in a first region while erase bias pass transistors are disposed in a second region. This segmentation spatially separates the two transistor types that were previously adjacent, thereby reducing wiring line load and interference while maintaining compact device area through optimized regional distribution.
2Device complexity
If bit line select transistors and erase bias pass transistors share wiring lines and drain regions, then device complexity is reduced, but erase operation efficiency deteriorates due to increased load
Solution Approach 1:
The patent extracts the erase bias pass transistors from the shared wiring configuration with bit line select transistors. By disposing erase bias pass transistors in a separate second region with dedicated wiring lines, the harmful shared load is removed while maintaining necessary device connectivity. This extraction resolves the conflict between simplified configuration and operational efficiency.
3Reliability
If the number of wiring lines is increased to separate transistor functions, then erase operation stability is improved, but device size increases
Solution Approach 1:
The patent applies local quality by creating region-specific transistor dispositions: bit line select transistors in a first region and erase bias pass transistors in a second region. This localized arrangement optimizes wiring line distribution for each transistor type's specific function, achieving stable erase operations through targeted separation rather than uniform expansion, thereby maintaining compact device size.
Data Source
AI summary
A semiconductor memory device includes a memory cell array; and a page buffer circuit coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction. The page buffer circuit includes a plurality of bit line select transistors coupled to the plurality of bit lines; a plurality of latches coupled to the plurality of bit line select transistors, respectively; and a plurality of erase bias pass transistors coupled to the plurality of bit lines, and configured to transfer an erase voltage to the bit lines. The plurality of erase bias pass transistors and the plurality of bit line select transistors are disposed in different regions, and are not adjacent to each other.