Page Buffer Latch Reuse for Triple Verify Programming

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Solution Overview

Problem

Existing memory devices face challenges in performing triple verify programming methods due to the increased size of the page buffer required for additional latches, which widens the threshold voltage distribution range and affects program operation speed.

Innovation Solution

A page buffer design with a sensing node, bit line voltage controlling circuit, and dual latches that perform sequential evaluation operations to store bit values, reducing the number of latches needed while maintaining efficient threshold voltage distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If three latches are used in the page buffer to store verify data for triple verify program method, then the verify operation can be performed using three verify voltages, but the size of the page buffer increases

Engineering Contradiction:

Improvetriple verify program capabilityVSAvoidpage buffer size

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The first latch is designed to serve multiple functions: it stores the first bit value during the first verify operation, then stores the second bit value during the second verify operation, and finally stores the third bit value during the third verify operation. This multi-functional design allows the page buffer to perform triple verify program operations without requiring three separate latches, thereby maintaining versatility while reducing circuit size.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The latch configuration is made dynamic by sequentially reusing the first latch for different bit values across three verify operations. The latch state changes over time to accommodate different verification stages, allowing the same hardware resource to adapt to different operational requirements without increasing the overall buffer size.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If the number of latches in the page buffer is increased to perform triple verify program, then the verify operation can be completed with three verify voltages, but the program operation speed decreases

Engineering Contradiction:

Improvetriple verify program capabilityVSAvoidprogram operation speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The first latch is precharged to a first initial value before the first verify operation begins. This preliminary preparation ensures that the latch is ready to immediately capture and store the first bit value without delay, enabling the triple verify program to proceed at high speed despite the sequential nature of the operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The first latch continuously maintains its precharged state and is ready to capture bit values throughout all three verify operations. By keeping the latch in a ready state and immediately capturing bit values as they become available during each verify operation, the system maintains continuous useful action without idle periods, thereby preserving program operation speed.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If three latches are used to store verify data, then complete verify information can be stored, but the circuit complexity increases

Engineering Contradiction:

Improveverify data storage completenessVSAvoidpage buffer circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

After the first latch stores the first bit value during the first verify operation, this initial value is discarded and the latch is recovered by precharging it to a new initial value for the second verify operation. This process repeats for the third verify operation. By discarding intermediate values and recovering the latch for reuse, the system maintains complete verify information storage capability while avoiding the need for additional latches, thus reducing circuit complexity.

Inventive Principle:

Principle #34Discarding and recovering

Data Source

PatentUS12609162B2Page buffer related to performing a program operation, memory device including a page buffer, and method of operating the page buffer

Publication Date: 2026.04.21 SK HYNIX INC

AI summary

Provided herein may be a page buffer. The page buffer includes a sensing node connected to a bit line, a bit line voltage controlling circuit configured to precharge the bit line during a verify operation, a sensing node voltage controller configured to precharge the sensing node while the bit line is precharged, a first latch connected to the sensing node, and configured to store a first bit value determined based on a first evaluation operation among bit values corresponding to a voltage level of the sensing node after the sensing node is precharged, and a second latch connected to the sensing node, and configured to store a second bit value determined based on a second evaluation operation after the first bit value is stored. The first latch stores the first bit value determined based on a third evaluation operation after the second bit value is stored in the second latch.