Memory Page Buffer Latches for Accurate Verify Loops

Solution Overview

Problem

Nonvolatile memory devices experience errors in verify operations and degradation of program end cells due to repeated program loops, leading to inefficiencies and potential data integrity issues.

Innovation Solution

A memory device and system that includes a control circuit and page buffers with latches to store verify results from previous loops, allowing for the determination of bit line voltages based on these stored results to optimize program loops and reduce errors and degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If repeated program loops are performed to program memory cells, then the number of programmed memory cells increases, but verify operation errors and program end cell degradation occur

Engineering Contradiction:

Improvenumber of programmed memory cellsVSAvoidverify operation accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by storing verify results from previous program loops (n-1 and n-2 loops) in latches before the current verify operation. These pre-stored results are used to determine the bit line voltage for the current verify operation, allowing the system to proactively adjust voltage based on historical data rather than reactively responding to errors after they occur. This prevents verify operation errors and cell degradation before they happen.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the stored verify results from previous loops to dynamically adjust the bit line voltage in the current loop. The control circuit continuously monitors verify results and modifies the bit line voltage accordingly, creating a closed-loop control system that adapts to changing cell states and prevents verify operation errors through real-time voltage adjustment.

Inventive Principle:

Principle #23Feedback

2Productivity

If repeated program loops are performed to program memory cells, then more memory cells are programmed, but program end cell degradation increases

Engineering Contradiction:

Improvenumber of programmed memory cellsVSAvoidprogram end cell threshold voltage

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by storing verify results from previous program loops (n-1 and n-2 loops) in latches before the current verify operation. These pre-stored results are used to determine the bit line voltage for the current verify operation, allowing the system to proactively adjust voltage based on historical data rather than reactively responding to errors after they occur. This prevents verify operation errors and cell degradation before they happen.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the stored verify results from previous loops to dynamically adjust the bit line voltage in the current loop. The control circuit continuously monitors verify results and modifies the bit line voltage accordingly, creating a closed-loop control system that adapts to changing cell states and prevents verify operation errors through real-time voltage adjustment.

Inventive Principle:

Principle #23Feedback

3Measurement precision

If verify voltage is applied to verify programmed memory cells, then program state can be confirmed, but verify operation errors occur due to threshold voltage degradation

Engineering Contradiction:

Improveprogram state verification accuracyVSAvoidverify operation accuracy

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the bit line voltage based on verify results from previous program loops. Instead of using a fixed verify voltage, the system modifies the bit line voltage parameter according to the degradation level indicated by historical verify results, thereby maintaining accurate verification despite threshold voltage degradation in program end cells.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback by using the stored verify results from previous loops to dynamically adjust the bit line voltage in the current loop. The control circuit continuously monitors verify results and modifies the bit line voltage accordingly, creating a closed-loop control system that adapts to changing cell states and prevents verify operation errors through real-time voltage adjustment.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12482524B2Memory device, operating method of memory device, and memory system

Publication Date: 2025.11.25 SK HYNIX INC

AI summary

A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines and a voltage generating circuit for selectively outputting a program voltage and a verify voltage; and a control circuit configured to control the peripheral circuit to perform a plurality of program loops each including a program voltage apply operation and a verify operation. Each of the plurality of page buffers may include: a first latch for storing a verify result according to the verify operation of an nth program loop among the plurality of program loops; and a second latch for storing a verify result according to the verify operation of an (n−1)th program loop among the plurality of program loops.