Page Buffer Voltage Adjustment for Memory Cell Programming Uniformity
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Solution Overview
Problem
Vertically stacked memory devices face programming speed variations due to differences in wiring lengths, leading to inefficient operation, as different memory cells have distinct programming speeds based on their connected wiring lengths.
Innovation Solution
A memory device with a page buffer that adjusts bitline voltages based on the distance of memory cells from a wordline cut region, supplying different voltages to bitlines connected to memory cells to compensate for programming speed differences, thereby ensuring uniform programming performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically stacked memory cells are used to increase cell area efficiency and decrease cell size, then memory device capacity and integration are improved, but programming speed varies substantially across different cells due to different wiring lengths
Solution Approach 1:
The patent applies local quality by providing different bitline voltages to different bitlines based on their specific characteristics. Memory cells connected to bitlines with longer wiring lengths receive higher bitline voltages, while those with shorter wiring lengths receive lower voltages. This localized voltage adjustment compensates for the wiring length differences and equalizes programming speeds across all memory cells in the vertically stacked structure.
2Reliability
If different bitline voltages are supplied to compensate for programming speed differences, then programming performance uniformity is improved, but page buffer circuit complexity increases
Solution Approach 1:
The patent implements dynamics by making the bitline voltage supplied by the page buffer dynamically adjustable based on the specific memory cell being programmed. The page buffer includes voltage selection circuitry that determines the appropriate bitline voltage level according to the wiring length characteristics of the target memory cell's bitline, allowing the system to adaptively compensate for variations without requiring complex dedicated circuitry for each bitline.
3Quantity of substance
If vertically stacked memory cells are used to achieve higher capacity, then storage capacity is improved, but threshold voltage distribution skew increases due to programming speed variations
Solution Approach 1:
The patent applies parameter changes by modifying the bitline voltage parameter based on the memory cell's position and wiring characteristics in the vertically stacked structure. By adjusting the voltage magnitude according to the specific bitline's wiring length, the patent compensates for programming speed variations and reduces threshold voltage distribution skew, thereby improving the overall precision and uniformity of memory cell characteristics while maintaining high storage capacity.
Data Source
AI summary
Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.