Page Buffer Voltage Amplification for Memory Read Speed
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Solution Overview
Problem
As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures are needed to address density and performance limitations in planar memory cells.
Innovation Solution
A page buffer is introduced in a memory device, comprising first, second, and third transistors, capacitance structures, and a latch circuit. This configuration allows for the amplification of a read margin voltage, thereby shortening the time required for read or verify operations in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled down to reduce die size, then manufacturing cost decreases and storage density increases, but process technology limitations and reliability issues worsen
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell scaling to three-dimensional vertically stacked memory cell architecture. By stacking multiple layers of memory cells vertically, the invention achieves higher storage density without further scaling down individual cell dimensions, thereby avoiding the reliability degradation associated with aggressive planar scaling.
2Quantity of substance
If vertically stacked memory cells are implemented to increase storage density, then storage density per unit area increases, but reliability concerns worsen due to aggressive scaling
Solution Approach 1:
The invention implements vertically stacked memory cell layers connected through memory strings, achieving three-dimensional storage density enhancement. This vertical stacking approach increases storage capacity per unit area while maintaining individual cell dimensions within reliable process technology ranges, thus mitigating reliability concerns associated with continued planar scaling.
3Productivity
If read operation time is reduced through voltage amplification, then productivity increases, but device complexity increases due to additional transistors and capacitance structures
Solution Approach 1:
The patent incorporates a page buffer that performs preliminary voltage amplification of the read margin signal before the sensing operation is completed. By amplifying the voltage signal in advance during the read operation, the invention reduces the total time required for data sensing and retrieval, thereby improving read productivity.
Solution Approach 2:
The invention introduces a page buffer as an intermediary component between the memory array and the sensing circuitry. This page buffer includes additional transistors and capacitance structures that mediate the read operation by amplifying voltage signals, enabling faster sensing while isolating the complexity from the core memory cell structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the page buffer significantly reduces the execution time of read and verify operations, enhancing the performance of memory devices by improving data sensing efficiency.
Implementation Method 1
The third transistor can amplify a read margin voltage at the second node
Implementation Method 2
a capacitance structure coupled to the first node
Data Source
AI summary
The present disclosure provides a memory device that includes a memory array and a page buffer. The memory array includes a plurality of memory cells coupled to a bit line of the memory array. The page buffer is coupled to the plurality of memory cells via the bit line to sense stored data in the memory cells. The page buffer includes first, second, and third transistors coupled to the bit line, first and second nodes, a capacitance structure coupled to the first node, and a latch circuit coupled to the bit line via the first transistor. First terminals of the first, second, and third transistors are coupled to the first node. A second terminal of the second transistor is coupled to the second node. The third transistor amplifies a read margin voltage at the second node. The page buffer shortens a time of a read operation or verify operation.