Page Buffer Voltage Control for Faster Bit Line Settling

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Solution Overview

Problem

Existing memory devices face challenges in efficiently shortening bit line settling time during sensing operations, which affects the overall performance and efficiency of data reading and writing processes.

Innovation Solution

The implementation of a page buffer control mechanism that adjusts the voltage level of a page buffer control signal before a sensing operation, utilizing a page buffer control switch and sense amplifier circuits to optimize the bit line settling time by applying a target voltage level based on the read voltage level of the word line, and performing an under drive operation to terminate the sensing operation before the word line settles at the read voltage level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the page buffer waits for the word line to fully settle at the read voltage level before performing the sensing operation, then the sensing accuracy is improved, but the bit line settling time increases

Engineering Contradiction:
Improvesensing accuracyVSAvoidbit line settling time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing the page buffer under drive operation before the word line fully settles at the read voltage level. The page buffer control signal is adjusted to a target voltage level in advance, based on the read voltage level, to prepare the bit line for the sensing operation while the word line is still settling. This allows the sensing operation to start earlier without compromising accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the voltage level parameter of the page buffer control signal from a default level to a target voltage level that is determined based on the read voltage level. This parameter adjustment allows the page buffer to operate in an under drive mode before the sensing operation, enabling earlier bit line preparation and reducing the settling time while maintaining sensing accuracy.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the page buffer performs the sensing operation immediately after programming, then the productivity is improved, but the data retention reliability deteriorates

Engineering Contradiction:
Improvesensing operation speedVSAvoiddata retention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary preparation of the page buffer control signal voltage level before the sensing operation begins. By adjusting the voltage level in advance based on the read voltage level, the system can initiate the sensing operation immediately after programming without waiting for full word line settling, thus improving productivity while maintaining data retention reliability through proper voltage preparation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250299744A1Page buffer related to a sensing operation, memory device including a page buffer, and operating method of a page buffer
Publication Date: 2025.09.25 SK HYNIX INC
  • US20250299744A1 patent drawing
  • US20250299744A1 patent drawing
  • US20250299744A1 patent drawing

AI summary

A memory device includes a memory cell array, a page buffer, and a bit line operation controller. The memory cell array includes a memory cell. The page buffer being connected to the memory cell through a bit line. The page buffer configured to perform a sensing operation of sensing program data stored in the memory cell. The bit line operation controller configured to control the page buffer to perform a page buffer under drive operation before the sensing operation. The page buffer including a latch circuit, a sense amp circuit, and a page buffer control switch. The latch circuit configured to store the program data. The sense amp circuit configured to perform the sensing operation. The page buffer control switch configured to connect the bit line and the sense amp circuit to each other.