Page Buffer Voltage Shifting for Flash Memory Interference

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Solution Overview

Problem

Highly integrated flash memory devices with smaller cells experience interference between adjacent cells due to capacitive coupling, leading to a widened threshold voltage distribution and decreased data retention in Single-Level Cell (SLC) and Multi-Level Cell (MLC) memory, necessitating a solution to reduce this interference.

Innovation Solution

The implementation of a memory device with a page buffer system that determines whether to shift the program verify (PV) voltage based on input data from both the target memory cell and neighboring cells, using signal paths between page buffers to process data and choose appropriate PV voltages for programming operations, thereby reducing coupling interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are highly integrated with smaller cell size, then storage capacity is improved, but interference between adjacent cells increases due to capacitive coupling

Engineering Contradiction:
Improvestorage capacityVSAvoidinterference between cells
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by determining whether to shift the PV voltage before performing the programming operation. The page buffer examines the data to be programmed and preemptively adjusts the PV voltage to compensate for anticipated interference from adjacent cells, thereby preventing the harmful effect rather than correcting it after the fact.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements parameter changes by dynamically adjusting the PV voltage level based on the data pattern and interference conditions. When interference is detected or anticipated, the system changes the PV voltage parameter (shifting it to a different level) to maintain adequate sensing window and ensure reliable programming despite the capacitive coupling between adjacent cells.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If PV voltage is shifted to reduce interference, then data retention is improved, but programming complexity increases

Engineering Contradiction:
Improvedata retentionVSAvoidprogramming complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The page buffer performs self-service by autonomously determining whether to shift the PV voltage based on the data it is holding and knowledge of adjacent cell states. This self-service capability eliminates the need for complex external control logic, as the page buffer independently makes the decision to adjust PV voltage, thereby improving reliability without proportionally increasing overall system complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system employs feedback by using information about adjacent cell data states to inform the PV voltage selection. The page buffer receives feedback regarding the data patterns in neighboring cells and uses this feedback to determine the appropriate PV voltage level, creating a closed-loop control mechanism that improves data retention while managing complexity through intelligent decision-making.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach maintains a sensing window by adjusting PV voltages, effectively reducing interference between memory cells and improving data retention by allowing for precise programming and reading operations.

Implementation Method 1

interference between the memory cells may occur due to capacitive coupling between nearby cells

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS9508455B2Memory device and operating method thereof for reducing interference between memory cells
Publication Date: 2016.11.29 MACRONIX INTERNATIONAL CO LTD
  • US9508455B2 patent drawing
  • US9508455B2 patent drawing
  • US9508455B2 patent drawing

AI summary

An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.