Page Table Cache Entry Combining for Higher TLB Hit Rate
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Solution Overview
Problem
The limited storage space of the translation lookaside buffer (TLB) results in a low hit rate, leading to increased memory access latency and overheads due to the need for time-consuming page table walks when TLB misses occur.
Innovation Solution
A method to increase the physical memory capacity covered by the page table cache by combining consecutive page table entries and using a combination flag bit to indicate entries participating in the combination, allowing for efficient matching and reducing the need for page table walks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TLB stores only one mapping relationship per entry, then the TLB structure is simple, but the physical memory capacity covered is limited and the hit rate is low
Solution Approach 1:
The patent combines multiple page table entries (PTEs) into a single TLB entry by merging consecutive PTEs that share the same physical page number. This allows one TLB entry to represent multiple virtual page numbers mapping to the same physical page, thereby increasing the physical memory capacity covered per TLB entry and improving the hit rate without significantly increasing structural complexity.
Solution Approach 2:
The patent makes a single TLB entry serve multiple functions by enabling it to represent multiple virtual-to-physical mappings through the combination of consecutive PTEs. The entry can match multiple input tags corresponding to different virtual page numbers, effectively making one entry perform the work of multiple traditional entries.
2Loss of time
If the TLB has limited storage space, then the device complexity is low, but the memory access latency increases due to frequent page table walks
Solution Approach 1:
By merging consecutive page table entries into a single TLB entry, the patent effectively increases the storage capacity of the TLB without physically expanding its size. Each combined entry covers a range of virtual page numbers, reducing the number of TLB misses and subsequent page table walks, thereby decreasing memory access latency.
Solution Approach 2:
The patent introduces a new dimension to TLB entries by adding the combination flag bit and enabling range-based matching. This allows the TLB to cover a larger address space in the same physical footprint by utilizing the combination dimension, effectively increasing storage capacity without adding more physical entries.
3Productivity
If consecutive page table entries are combined, then the physical memory capacity covered per entry increases, but the matching complexity increases
Solution Approach 1:
The patent segments the matching process into two stages: first, quick matching of the input tag against the entry tag using the combination flag bit to determine the matching range; second, verifying whether the input tag falls within the combined range. This segmentation reduces the overall matching complexity by separating the common case (single PTE) from the combined case (multiple PTEs).
Solution Approach 2:
The patent performs preliminary action by pre-calculating and storing the entry tag that represents the combined range of virtual page numbers in the TLB entry. This allows the matching logic to quickly determine whether an input tag might match without having to examine all individual PTEs, thereby reducing matching complexity while maintaining high translation efficiency.
Data Source
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AI summary
This application provides a physical address determining method and apparatus, a computing device, and a storage medium, and pertains to the field of computer technologies. In the method, an input tag generated based on a virtual page number in a first virtual address is matched with a plurality of entries in a page table cache. If the input tag successfully matches a first entry in the plurality of entries, and a combination flag bit in the first entry indicates that a page table entry corresponding to the first entry is a combined entry, a physical address corresponding to the first virtual address is determined based on the virtual page number in the first virtual address and an entry tag and a physical page number in the first entry. In the foregoing method, one entry in the page table cache corresponds to at least one page table entry, so that a physical memory capacity covered by the entry in the page table cache can be increased, to improve a hit rate of the page table cache, reduce a page table walk, and reduce memory access latency and memory access overheads.