Page-Data-Copy Memory Architecture for AI Processing Bandwidth
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Solution Overview
Problem
Conventional DRAM cell array architectures face limitations in prefetch number, leading to tradeoffs between power consumption, access energy efficiency, and bank area, while inter-chip interface bandwidth and power consumption issues restrict system performance.
Innovation Solution
A memory-based apparatus using a page-data-copy scheme with page registers and a processing block, enabling conditional data access and arithmetic operations, and embedding these components in a semiconductor chip or across multiple chips for efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional cell array architecture is used, then bank area is limited, but prefetch number reaches its limitation
Solution Approach 1:
The memory bank is divided into multiple cell array sections, each capable of independent prefetch operations. This segmentation allows the system to achieve higher overall prefetch numbers without proportionally increasing the total bank area, as each section can be optimized independently.
Solution Approach 2:
The patent introduces a multi-dimensional data access architecture that extends beyond traditional single-plane prefetching. By organizing memory access across multiple dimensions (different cell array sections, bit line sections, and page buffers), the system achieves enhanced prefetch capability without linearly increasing physical bank area.
2Productivity
If prefetch number is increased, then data access bandwidth is improved, but power consumption increases
Solution Approach 1:
Data is prefetched and stored in page buffers before actual processing is needed. This preliminary action allows the main processing logic to access already-prepared data, reducing the need for high-power operations during critical processing paths while maintaining high bandwidth throughput.
Solution Approach 2:
Page buffers serve as intermediary storage between the cell array sections and the processing logic. This intermediary layer enables efficient data transfer and caching, allowing high bandwidth access patterns to be achieved with lower overall power consumption by reducing redundant memory access operations.
3Productivity
If inter-chip interface is used for data processing, then access bandwidth is achieved, but power consumption and heat dissipation increase
Solution Approach 1:
Multiple cell array sections and processing elements are merged into a unified on-chip architecture that performs data processing locally. This consolidation eliminates the need for inter-chip interfaces for many data processing operations, significantly reducing power consumption and heat dissipation while maintaining high access bandwidth through internal high-speed interconnects.
Solution Approach 2:
The memory system is designed to perform data processing operations self-sufficiently on-chip using integrated processing elements and page buffers. This self-service capability reduces dependence on external inter-chip interfaces, thereby minimizing the power consumption and heat generation associated with off-chip data transfer.
Data Source
AI summary
Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.