Page Decompression Accelerator Using Speculative DMA Descriptors
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Solution Overview
Problem
Current systems face significant latency issues in page decompression due to the sequential nature of the decompression process, which limits processing speed and increases overall decompress latency, especially when dealing with larger data sets where the compressed tier can have a greater adverse impact on performance.
Innovation Solution
The implementation of a speculative decompress job submission mechanism that issues a decompress operation to an accelerator using only the source address, allowing parallel execution with the determination of the destination address, and using a 'torn' new descriptor to define multiple related jobs for a hardware accelerator, enabling early decompression and reducing OS-related overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional sequential decompression process is used, then processing accuracy is maintained, but decompression latency increases significantly
Solution Approach 1:
The patent applies preliminary action by submitting the first descriptor (speculative decompress job) to the hardware accelerator before the destination address is determined. This allows the decompression process to start in advance, hiding the time required for OS memory management operations. The accelerator begins processing the compressed page immediately using only the source address, while the destination address is determined subsequently through page fault handling or free page allocation.
Solution Approach 2:
The patent segments the decompression process into two independent phases represented by two descriptors: (1) a speculative decompress job that initiates decompression without a destination address, and (2) a second descriptor that provides the destination address after OS memory management completes. This segmentation allows parallel execution of decompression and memory management tasks, reducing overall latency.
2Productivity
If destination address determination is performed before decompression, then memory management accuracy is ensured, but processing speed decreases
Solution Approach 1:
The patent introduces an intermediary mechanism where the hardware accelerator processes the first descriptor (speculative job) independently of the OS memory management path. The accelerator acts as an intermediary that can begin decompression using only the source address from the first descriptor, while the destination address is determined later by the OS through page fault handling or free page allocation. This intermediary approach allows parallel execution without compromising memory management correctness.
Solution Approach 2:
The system performs preliminary decompression action through the first descriptor before the destination address is finalized by the OS. The hardware accelerator starts processing immediately with the source address available, while the destination address determination happens in parallel through OS memory management operations such as page fault handling or free page allocation from a free page list.
3Adaptability or versatility
If OS memory management operations are performed sequentially, then memory allocation accuracy is maintained, but accelerator utilization decreases
Solution Approach 1:
The patent applies dynamics by making the descriptor processing flexible and adaptive. The first descriptor is processed dynamically without requiring a destination address, allowing the accelerator to start work immediately. The system adapts to different OS memory management paths (page fault handling, free page allocation) by accepting the destination address at a later stage through a second descriptor. This dynamic approach allows the accelerator to remain busy while the OS performs memory management operations at its own pace.
Data Source
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AI summary
Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.