Page Decompression Accelerator Using Torn Descriptors
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Solution Overview
Problem
Existing decompression processes in computer systems suffer from high latency due to the sequential nature of the decompression process and the overhead involved in determining the destination address for decompressed data, which limits processing speed and efficiency.
Innovation Solution
A method involving the use of a 'torn' descriptor system where a first descriptor is sent with a missing destination address, allowing the decompression to occur in a buffer, and a second descriptor is used to write the decompressed data to the correct location, thereby reducing the time needed to find a free memory page and overlapping decompression with data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the decompression process is performed sequentially with traditional descriptor-based addressing, then the destination address can be determined accurately, but the decompression latency increases due to the time required to find a free memory page and the sequential processing nature
Solution Approach 1:
The patent applies preliminary action by pre-allocating buffer memory space and preparing descriptor templates before decompression is actually needed. The system pre-sets up the decompression pipeline and memory buffers in advance, so when decompression jobs arrive, they can be processed immediately without waiting for memory allocation or descriptor preparation, thus reducing decompression latency while maintaining accurate destination addressing
Solution Approach 2:
The patent segments the decompression process into independent parallel stages: descriptor validation, memory buffer allocation, decompression execution, and result writing. By dividing the sequential process into concurrent segments that can be processed in parallel, the system reduces overall decompression latency while maintaining processing accuracy through staged validation at each segment
2Productivity
If the system waits to determine the destination address before initiating decompression, then memory management accuracy is maintained, but the overall processing efficiency and accelerator utilization decrease
Solution Approach 1:
The patent introduces an intermediary buffer memory layer between the decompression accelerator and the final destination memory. The intermediary buffer temporarily holds decompressed data with placeholder addressing, allowing the accelerator to operate at full utilization without waiting for final destination address determination. A separate address resolution process then maps the intermediary buffer contents to the correct final destinations, maintaining memory management accuracy while maximizing accelerator productivity
Solution Approach 2:
The system implements self-service by enabling the decompression accelerator to autonomously write results to pre-allocated intermediary buffers using placeholder descriptors, without requiring external validation of final destination addresses at the time of decompression. The address resolution mechanism subsequently self-corrects the mapping, allowing the accelerator to maintain high utilization while the system as a whole preserves memory management accuracy
Data Source
AI summary
Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.