Page Fault Handling Offload Engine for NVM Latency Reduction
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Solution Overview
Problem
Emerging non-volatile memories (NVM) with low latency pose challenges in page fault handling due to increased context switch overhead, which is significant compared to traditional storage devices, leading to higher latency in page fault operations.
Innovation Solution
A page fault handling offload engine (POE) is implemented, utilizing a pre-allocation mechanism, enhanced hardware page walker, and kernel background threads to reduce overhead by pre-allocating pages and moving operations out of the page fault critical path, thereby minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If kernel-based page fault exception handling is used, then page faults can be handled with traditional storage devices (SSD/HDD), but context switch overhead becomes significant when using emerging NVM, increasing total access latency
Solution Approach 1:
The patent extracts the page fault handling operations from the kernel exception path and moves them to user space. A page fault handling library is implemented that can be called directly from user space applications, eliminating the need for context switches to kernel space for page fault handling. The library performs page allocation, mapping, and data transfer operations entirely in user space, thereby removing the context switch overhead that becomes significant with NVM.
Solution Approach 2:
The patent introduces a page fault handling library as an intermediary between the application and the operating system kernel. This library acts as a mediator that handles page faults in user space by managing page allocation, memory mapping, and data transfer without requiring kernel intervention for each page fault. The library communicates with the kernel only when necessary, reducing context switch frequency while maintaining system reliability.
2Quantity of substance
If lazy allocation is used to reduce memory usage, then multiple applications can execute concurrently, but page fault handling operations increase when memory is exhausted requiring swapping
Solution Approach 1:
The patent implements preliminary action by pre-allocating pages in the page pool before they are needed. When memory is available, pages are pre-allocated and stored in a page pool data structure, so that when a page fault occurs, the page is already ready and can be quickly mapped without requiring allocation operations during the page fault handling critical path. This reduces the number of operations performed during page faults and improves handling throughput.
Solution Approach 2:
The patent maintains continuity of useful action by keeping a pool of pre-allocated pages ready for immediate use. Instead of allocating pages on-demand during page faults, the system continuously maintains a supply of available pages in the page pool, ensuring that page fault handling can proceed without interruption or additional allocation overhead. This continuous availability of pages improves productivity while lazy allocation still allows multiple applications to share memory resources.
3Loss of time
If pre-allocation of pages is performed, then page fault critical path latency is reduced, but memory is consumed before pages are actually needed
Solution Approach 1:
The patent applies partial action by pre-allocating only a portion of the total possible pages - specifically, a page pool of configurable size is maintained rather than pre-allocating all possible pages. This partial pre-allocation provides enough pages to handle typical page fault loads without consuming excessive memory. The page pool size can be tuned to balance between reducing page fault latency and minimizing memory consumption, allowing the system to perform excessive pre-allocation only when beneficial.
Data Source
AI summary
Methods, systems, and computer readable media for performing page fault handling are disclosed. According to one method, the method includes: after a translation lookaside buffer (TLB) miss associated with a virtual memory page occurs, identifying, in a page table, a page table entry (PTE) associated with the virtual memory page; determining, using a first indicator in the PTE, that the virtual memory page is not present in a main memory; determining, using a second indicator in the PTE, that the virtual memory page is associated with a valid memory address and that the virtual memory page is capable of using pre-allocated pages; obtaining, from a pre-allocation table, a page frame number associated with a pre-allocated page; and updating the PTE to indicate the page frame number.