Page Memory Architecture for High Density Bit-Plane Storage
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Solution Overview
Problem
Existing SIMD array architectures for image processing face challenges in achieving high processing throughput while maintaining high density and bandwidth for bit-plane data storage, with previous approaches either sacrificing PE density for high bandwidth or vice versa.
Innovation Solution
A digital data processing system with a page memory that balances bandwidth and density by using a page memory width of ⅛th bit-plane, distributed among page units, allowing for concurrent subframe I/O and paging with low latency and minimal foreground cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If page memory width is increased to improve bandwidth, then paging bandwidth is improved, but device complexity and area increase
Solution Approach 1:
The page memory is segmented into multiple page units, each handling a portion of the bit-plane data. This segmentation allows the system to achieve high bandwidth by parallel processing across multiple units while keeping individual unit complexity manageable. Each page unit operates independently on its assigned data portion, enabling concurrent operations without requiring a monolithic complex memory structure.
2Productivity
If PE density is increased to improve processing throughput, then processing throughput is improved, but bandwidth for bit-plane data storage decreases
Solution Approach 1:
The system introduces a hierarchical memory structure that adds a temporal dimension to data storage. Recent bit-plane data is stored in on-chip page memory for fast access, while older data is archived in off-chip memory. This dimensional addition allows high PE density without sacrificing bandwidth, as the bandwidth constraint only applies to the recent data window that fits in on-chip memory, not the entire data history.
3Quantity of substance
If page memory width is set to 1/8th bit-plane to balance density and bandwidth, then density is improved, but paging latency increases
Solution Approach 1:
The system performs preliminary action by pre-loading recent bit-plane data into on-chip page memory before it is needed for processing. This allows the actual processing to begin immediately without waiting for data retrieval, effectively hiding the paging latency. The page memory is continuously updated with recent data, ensuring that when processing occurs, the data is already available for immediate use.
4Speed
If data path width between primary and secondary storage is increased to improve bandwidth, then bandwidth is improved, but device complexity increases
Solution Approach 1:
The data path between primary and secondary storage is merged with the existing SIMD array interconnect structure. The same physical interconnect that distributes instructions and data within the PE array is also used to transfer data between memory levels. This merging eliminates the need for separate dedicated data paths, achieving high bandwidth without adding proportional complexity, as the existing infrastructure is reused for dual purposes.
Data Source
AI summary
In an image processing system, high density storage of bit-plane data is provided in a secondary or page memory as well as high bandwidth access to the data by an image processor. The page memory provides storage of data not currently being processed. The page memory may also be part of a system that provides input and output of image data to and from the image processor. The image data may be handled outside the image processor in a packed pixel form and be converted between that form and bit-line form which the page memory stores during input and output. The bit-line data may be gathered into bit-planes for use by the image processor during movement of data from the page memory to the processing logic.