Page Request Interface Handler for Cached Address Translation Misses
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Solution Overview
Problem
The need for continuous address translation requests to a translation agent (TA) in memory sub-systems, particularly in NVMe devices, leads to performance bottlenecks in terms of speed, latency, and quality-of-service, due to increased I/O traffic and inefficient handling of memory commands and DMA operations.
Innovation Solution
Implementing an address translation cache (ATC) within the controller to store address translations for future access, and incorporating a page request interface (PRI) handler to automate page miss requests, reducing the need for pinning large amounts of host memory and optimizing DMA operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address translation requests are continuously sent to a translation agent (TA) in memory sub-systems, then address translation functionality is maintained, but performance bottlenecks occur in terms of speed, latency, and quality-of-service due to increased I/O traffic
Solution Approach 1:
The patent implements an address translation cache (ATC) that pre-stores address translation mappings in the memory sub-system controller. By caching translations locally before they are needed, the system eliminates the need for continuous real-time requests to the translation agent, thereby maintaining address translation functionality while dramatically reducing I/O traffic and improving performance metrics such as speed and latency.
Solution Approach 2:
The address translation cache acts as an intermediary component between the memory sub-system controller and the translation agent. Instead of direct communication between the controller and TA for every address translation request, the ATC mediates by intercepting requests and serving cached translations when available, thus reducing the frequency of I/O operations to the translation agent while maintaining translation accuracy.
2Reliability
If host memory is pinned to support DMA operations and address translation, then address translation requests can be handled, but large amounts of host memory must be reserved, reducing memory availability
Solution Approach 1:
The patent segments the address translation functionality from the host memory space by implementing a dedicated address translation cache within the memory sub-system controller. This segmentation allows the controller to maintain its own local translation tables without requiring corresponding host memory pages to be pinned, thereby preserving host memory availability while maintaining full address translation handling capability.
Solution Approach 2:
The address translation cache serves as an intermediary that eliminates the need for host memory pinning. By storing translation mappings locally in the controller's ATC, the system mediates between DMA operations and host memory management, allowing the controller to perform address translations independently without reserving host memory resources.
Data Source
AI summary
A processing device includes host interface circuitry to interact with a host system and an address translation circuit to handle address translation requests to the host system from host interface circuits. The address translation circuit includes a cache to store address translations associated with the address translation requests for future access by host interface circuits. A page request interface (PRI) handler tracks translation miss messages received from the host interface circuits, each translation miss message including a virtual address of a miss at the cache. The PRI handler removes duplicate translation miss messages having an identical virtual address and creates page miss requests from non-duplicate translation miss messages that are categorized into page request groups, each page request group corresponding to a host interface circuit of the host interface circuits. The PRI handler queues the page request groups to be sent to a translation agent of the host system.