Page Table Entry Access States for Selective Translation Caching
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Solution Overview
Problem
Existing data processing systems inefficiently utilize address translation caches, leading to performance degradation due to caching of infrequently used translations and unnecessary page table walks.
Innovation Solution
Implement state tracking circuitry to maintain access states of page table entries, controlling caching in address translation caches based on access frequency and usage, suppressing caching for infrequently used entries and allowing caching for frequently used ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address translations are cached in the address translation cache, then translation speed is improved, but cache memory is wasted on infrequently used translations
Solution Approach 1:
The patent implements dynamic caching control by introducing access state tracking (non-accessed, first-accessed, multi-accessed states) that changes based on usage patterns. The caching behavior is not static but adapts to the actual access frequency of page table entries, allowing the system to optimize between translation speed and cache memory utilization based on real-time usage characteristics.
Solution Approach 2:
The patent changes the parameter of caching eligibility based on the access state of page table entries. By tracking whether an entry has been accessed once or multiple times, the system dynamically adjusts which translations are cached, transforming the caching strategy from a static all-or-nothing approach to a selective parameter-based approach that optimizes memory utilization.
2Ease of operation
If all page table entries are cached, then translation access is simplified, but frequently needed cache capacity is reduced
Solution Approach 1:
The patent applies local quality by treating different page table entries differently based on their individual access patterns. Instead of uniformly caching all translations, the system selectively caches only those entries that have been accessed multiple times, giving different caching treatment to different parts of the address space based on their specific usage characteristics.
Solution Approach 2:
The patent implements partial caching action by caching only a subset of page table entries - specifically those in the multi-accessed state - rather than caching all translations. This partial approach ensures that cache capacity is concentrated on frequently used translations while avoiding waste on infrequently used ones.
3Productivity
If address translation cache is used, then system performance is improved, but unnecessary page table walks occur due to caching infrequently used translations
Solution Approach 1:
The patent implements feedback mechanisms by tracking access states of page table entries and using this information to control caching behavior. The system monitors whether translations are frequently or infrequently used and adjusts caching accordingly, creating a feedback loop that prevents unnecessary page table walks by ensuring only relevant translations are cached.
Solution Approach 2:
The patent performs preliminary action by pre-tracking access patterns of page table entries before deciding whether to cache them. By monitoring access states (non-accessed, first-accessed, multi-accessed) in advance, the system prepares the caching decision based on actual usage evidence, preventing premature caching of translations that would not be beneficial.
Data Source
AI summary
An apparatus for address translation is provided in order to translate virtual addresses used by devices in a data processing system into physical addresses for accessing memory. In accordance with the techniques disclosed herein, state tracking circuitry is provided to maintain the state of a page table entry that specifies such address translations. The state can be used to assess whether or not the address translation entry is worth storing in an address translation cache provided for faster access of previously used address translations. Accordingly, the techniques disclosed herein allow for more efficient use of the limited capacity available in the address translation cache as well as additional uses of a page table entry's state.