Page Table Cache Coherency Indicator for Heterogeneous Processors
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Solution Overview
Problem
Existing cache coherency mechanisms in computing devices with multiple heterogeneous processors become overwhelmed, leading to delayed responses and increased communication traffic, and software coherency mechanisms are error-prone and costly to implement.
Innovation Solution
The use of a page table with a cache coherency indicator to manage data access by specifying which types of processors have access to memory pages, reducing the need for hardware coherence directory lookups and improving efficiency by preventing unauthorized access and caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware cache coherency mechanisms are used in computing devices with multiple heterogeneous processors, then cache coherency is maintained, but communication buses and hardware coherency directories become overwhelmed with traffic, causing delayed responses and reduced productivity
Solution Approach 1:
The patent segments the coherency management function by introducing coherency indicators in page table entries that identify which processor types may access specific memory pages. This segmentation allows the system to divide coherency enforcement into page-level granularity, reducing the need for comprehensive hardware directory lookups and decreasing communication bus traffic while maintaining coherency where required.
Solution Approach 2:
The patent performs preliminary coherency management by setting coherency indicators in page table entries during memory management operations. This preliminary action pre-establishes which processor types can access which memory pages, allowing processors to make access decisions without real-time hardware directory queries, thereby reducing latency and improving computational operation speed.
2Reliability
If hardware cache coherency mechanisms are used, then cache coherency is maintained, but the complexity of the system increases due to inundated communication buses and hardware coherency directories
Solution Approach 1:
The patent extracts the coherency management information from the hardware coherency directory system and embeds it directly in the page table entries. This extraction removes the burden of maintaining comprehensive coherency state information in hardware directories, simplifying the overall system architecture while preserving coherency guarantees through the page table-based indicators.
3Productivity
If software cache coherency mechanisms are used, then the load on hardware coherency mechanisms is reduced, but the mechanisms become error-prone and expensive to implement in software applications
Solution Approach 1:
The patent introduces page table coherency indicators as an intermediary mechanism between hardware and software coherency management. This intermediary provides a structured, hardware-supported approach that is more reliable than pure software mechanisms while placing less load on hardware coherency directories than traditional hardware-only approaches. The page table serves as the mediator that encodes coherency policies in a manageable and error-resistant manner.
Data Source
AI summary
The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.