Page Table Coherency Unit for Automatic Cache Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current computing systems face performance lags and data discrepancies due to the need for explicit cache maintenance operations when page table data is modified across multiple processing devices, and input/output-coherent accesses experience unbounded latencies, which are not suitable for real-time applications.
Innovation Solution
Implementing a page table coherency unit that intercepts cache invalidate signals, issues cache maintenance commands, and writes modified page table data to shared memory, ensuring coherent copies across caches while reducing the need for explicit synchronization operations and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If explicit cache maintenance operations are performed to maintain page table coherency across multiple processing devices, then data coherency is maintained, but software maintenance costs increase and performance slows down
Solution Approach 1:
The patent introduces a page table coherency unit as an intermediary component that automatically manages cache coherency for page table data. This unit intercepts page table cache invalidate signals, executes cache maintenance operations, and coordinates updates across multiple processing devices, eliminating the need for software to perform explicit cache maintenance operations while ensuring data coherency is maintained.
2Reliability
If IO-coherent accesses are used for SMMU page table lookups, then shared memory access is achieved, but unbounded quality of service latencies occur that cannot be tolerated by real-time clients
Solution Approach 1:
The patent implements preliminary action by pre-establishing coherent copies of page table data in the caches of multiple processing devices before actual memory access operations occur. The page table coherency unit proactively manages the validity and synchronization of these cached copies, ensuring that when real-time clients need to access shared memory, they can do so with bounded latency through their local coherent caches rather than experiencing unbounded delays from IO-coherent accesses.
Data Source
AI summary
Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.