Page Table Data Fetch Width Indicator for Cache Adaptation
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Solution Overview
Problem
Computer systems face inefficiencies in data fetching due to fixed cache line sizes that do not adapt to the specific data access patterns of different applications, leading to suboptimal performance in terms of cache utilization and resource utilization.
Innovation Solution
Incorporating a data fetch width indicator in the page table that dynamically adjusts the cache line size based on application-specific requirements, monitored through a counter management module that updates the fetch width indicator based on access patterns, allowing for wider or narrower fetches as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed cache line sizes are used, then device complexity is reduced, but cache utilization and system performance deteriorate
Solution Approach 1:
The patent embeds a data fetch width indicator field within the existing page table entry structure, nesting the adaptive functionality inside the conventional page table framework. This allows the system to incorporate variable cache line size support without adding separate complex control structures, as the indicator is nested within the page table entry itself.
Solution Approach 2:
The patent changes the parameter of cache line size from a fixed value to a variable value determined by the data fetch width indicator in the page table entry. This allows the system to adapt cache line size dynamically based on application requirements while maintaining a relatively simple implementation by leveraging existing page table infrastructure.
2Productivity
If fixed cache line sizes are used, then ease of operation is maintained, but productivity and resource utilization deteriorate
Solution Approach 1:
The system enables self-service by allowing the page table entry's data fetch width indicator to automatically determine the appropriate cache line size without requiring external control logic. The fetch control mechanism uses this indicator to autonomously adjust data fetching width, improving productivity while keeping the control mechanism simple.
Solution Approach 2:
The page table entry structure is enhanced to serve multiple functions: traditional address translation plus storing the data fetch width indicator. This multi-functionality allows the same structure to control both memory management and data fetching optimization, improving productivity without adding separate specialized control structures.
3Adaptability or versatility
If application-specific cache line sizes are implemented, then cache utilization improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by allowing different data fetch width indicators in different page table entries, enabling application-specific optimization at the local level of individual memory pages. Each page can have its own optimized cache line size without affecting other pages, achieving adaptability while keeping the overall system manageable through localized control.
Data Source
AI summary
Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.