Page Table Entry Extension for Larger Virtual Memory Pages
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Solution Overview
Problem
The effectiveness of caching techniques in virtual memory systems is limited by fixed page or frame sizes, leading to increased TLB miss rates and reduced memory management efficiency.
Innovation Solution
Implementing a method to align a fixed number of smaller pages to create a larger page size, using a bit or flag in page table entries to indicate the combined page size, and utilizing translation lookaside buffers (TLBs) to enhance address translation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed page sizes (e.g., 4K, 4M) are used in virtual memory schemes, then memory protection and address translation are simplified, but caching effectiveness is limited and TLB miss rates increase
Solution Approach 1:
The patent segments the page size into multiple granularity levels by allowing dynamic configuration of page sizes (e.g., 4K, 64K, 4M) within the same virtual memory scheme. This segmentation enables fine-grained control over cache lines and TLB entries, improving caching effectiveness without fundamentally changing the address translation mechanism.
Solution Approach 2:
The patent introduces dynamic page size configuration where the page size can be adjusted based on access patterns and workload requirements. The system can dynamically switch between different page sizes (4K, 64K, 4M) to optimize caching performance, making the memory management scheme adaptive rather than static.
2Device complexity
If larger page sizes (e.g., 4M) are used, then fewer pages need to be managed, but granularity is reduced and TLB miss rates increase for small memory allocations
Solution Approach 1:
The patent segments the page size into multiple granularity levels by allowing dynamic configuration of page sizes (e.g., 4K, 64K, 4M) within the same virtual memory scheme. This segmentation enables fine-grained control over cache lines and TLB entries, improving caching effectiveness without fundamentally changing the address translation mechanism.
Solution Approach 2:
The patent changes the page size parameter dynamically based on the specific memory allocation requirements. Instead of using a fixed page size, the system can adjust the page size parameter to match the workload needs, optimizing both management complexity and allocation granularity for different scenarios.
3Measurement precision
If smaller page sizes (e.g., 4K) are used, then granularity is improved, but the number of pages increases and TLB miss rates increase
Solution Approach 1:
The patent segments the page size into multiple granularity levels by allowing dynamic configuration of page sizes (e.g., 4K, 64K, 4M) within the same virtual memory scheme. This segmentation enables fine-grained control over cache lines and TLB entries, improving caching effectiveness without fundamentally changing the address translation mechanism.
Solution Approach 2:
The patent introduces dynamic page size configuration where the page size can be adjusted based on access patterns and workload requirements. The system can dynamically switch between different page sizes (4K, 64K, 4M) to optimize caching performance, making the memory management scheme adaptive rather than static.
Data Source
AI summary
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.