Page Table Manager Offloading Memory Accesses
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Solution Overview
Problem
Modern virtual machine systems employing 2-dimensional page table walks require excessive memory accesses, leading to suboptimal performance due to memory latency, as each lookup must complete before the next can be issued, resulting in a significant increase in memory access counts compared to systems without virtual machines.
Innovation Solution
Implementing a page table management device or node to offload page table access and maintenance functions from the CPU, allowing for 1-dimensional page table walks and reducing memory contention, thereby improving CPU efficiency and reducing the number of memory accesses required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 2-dimensional page table walks are implemented to support virtual machines, then virtual machine functionality is achieved, but memory access count increases significantly
Solution Approach 1:
The patent segments the page table management functionality by introducing a dedicated page table management device separate from the CPU. This segmentation allows the CPU to offload page table walk operations to the specialized device, thereby reducing the memory access burden on the CPU while maintaining virtual machine functionality through coordinated operation between the CPU and page table management device.
Solution Approach 2:
The patent introduces a page table management device as an intermediary between the CPU and memory systems. This intermediary handles page table walk operations, translating virtual addresses to physical addresses without requiring the CPU to perform each memory access sequentially, thus reducing the overall memory access count while preserving virtual machine operation.
2Loss of information
If 2-dimensional page table walks are performed, then virtual memory translation is achieved, but memory latency impact increases
Solution Approach 1:
The page table management device performs self-service by autonomously handling page table walk operations without requiring CPU intervention for each translation. The device maintains its own page table structures and can perform translations independently, reducing the time impact of memory latency on the CPU while ensuring accurate virtual to physical address translation.
Solution Approach 2:
The patent implements preliminary action by having the page table management device pre-load and maintain page table entries in accessible memory structures. This allows the device to quickly retrieve translation information without requiring the CPU to perform sequential memory accesses, thereby reducing memory latency impact while maintaining accurate address translation.
3Ease of operation
If page table management is performed by the CPU, then control is centralized, but CPU efficiency decreases
Solution Approach 1:
The patent extracts page table management functions from the CPU and places them in a dedicated page table management device. This extraction maintains centralized control over virtual memory operations while freeing the CPU from the burden of handling each page table walk, thereby improving CPU efficiency without sacrificing operational control.
Solution Approach 2:
The page table management device provides multi-functionality by handling various page table operations including address translation, page fault handling, and memory management tasks. This universal device can service multiple virtual machines and handle diverse memory management requirements, maintaining centralized control while improving overall system productivity by dedicating specialized hardware to these functions.
Data Source
AI summary
The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.