Hierarchical Page Table Translation Circuitry Prefetching
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Solution Overview
Problem
Current memory address translation processes, particularly in data processing apparatuses, face inefficiencies due to the need for multiple stage translations and the limited capacity of translation lookaside buffers (TLBs), which can lead to time-consuming accesses to main memory and stalls during page table walks.
Innovation Solution
The implementation of memory address translation circuitry that organizes translation information in a hierarchy of page table levels, allowing entries to be stored and accessed as groups within a single memory retrieval operation, with each entry pointing to the next lower level table, and utilizing prefetching to speculatively populate cache lines with entries from multiple level tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiple stage translation process is used via an intermediate physical address, then memory access control and isolation between programs are improved, but translation time and processing complexity increase
Solution Approach 1:
The page table hierarchy segments the translation process into multiple levels (level 0, level 1, level 2 tables), where each level handles a portion of the address translation. This segmentation allows the system to maintain multiple stage translation for security while optimizing performance through hierarchical access patterns and prefetching mechanisms.
Solution Approach 2:
The system performs preliminary actions by prefetching page table entries from lower levels before they are actually needed during address translation. The prefetch circuitry anticipates future translation needs and loads required page table data in advance, reducing translation time when the actual translation is needed.
2Device complexity
If the TLB capacity is limited, then device complexity and cost are reduced, but translation speed and productivity decrease due to more frequent main memory accesses
Solution Approach 1:
The patent introduces a new dimension to the TLB architecture by implementing a hierarchical page table structure with multiple levels. Instead of a single-level TLB, the system uses level 0, level 1, and level 2 tables arranged in a hierarchy, allowing more efficient use of limited TLB capacity through multi-level caching and prefetching mechanisms.
Solution Approach 2:
The prefetch circuitry performs preliminary actions by speculatively loading page table entries from lower levels before they are needed. This anticipatory loading reduces the impact of limited TLB capacity by ensuring that frequently accessed page table data is already available in the hierarchy, maintaining high translation speeds despite TLB constraints.
3Loss of information
If page table entries are accessed sequentially through multiple memory operations, then complete translation information is obtained, but processing time and stalls increase
Solution Approach 1:
The system performs preliminary actions by prefetching page table entries from lower levels before they are actually needed during address translation. The prefetch circuitry anticipates future translation needs and loads required page table data in advance, reducing translation time when the actual translation is needed.
Solution Approach 2:
The hierarchical page table structure enables continuous useful action by allowing parallel prefetching operations to proceed concurrently with active address translations. Multiple page table entries can be loaded in parallel from different levels, ensuring that the translation process never stalls waiting for data, thus maintaining continuous productive operation.
Data Source
AI summary
Circuitry comprises memory address translation circuitry to access memory circuitry storing translation information defining memory address translations from input memory addresses to respective output memory addresses; in which the translation information stored by the memory circuitry comprises a hierarchy of page table levels from a highest page table level to a lowest page table level, each page table level having one or more level tables each comprising two or more entries, in which an entry of a level table at a page table level other than a last page table level of the hierarchy points to a level table at a next lower page table level in the hierarchy; the memory address translation circuitry being configured to select an entry of a level table at each page table level according to a selection value, the selection value being dependent upon a portion, applicable to that page table level, of a given input memory address; in which the memory circuitry is configured to store entries as groups of entries, a group of entries being accessible by a single memory retrieval operation; and in which, for at least a subset of the page table levels, a group of entries stored by the memory circuitry comprises a set of entries from two or more respective level tables.