Page Table Walker Access to Multilevel Page Table Entries
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Solution Overview
Problem
Existing methods for accessing page table entries in multilevel page tables require recursive mapping, reducing the number of available entries and leading to decreased efficiency due to cached mappings being usable only for subsequent recursive operations.
Innovation Solution
Optimize access by determining a specific number of page table walk levels (T) to traverse, based on the memory access instruction, allowing direct identification of a physical memory address without full recursive traversal, thus conserving page table entries and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If recursive mapping is used to access page table entries, then the page table entry can be accessed, but the number of available page table entries is reduced
Solution Approach 1:
The patent extracts the page table entry access functionality from the recursive mapping mechanism. Instead of requiring the software process to perform recursive mapping operations, the MMU automatically performs a truncated page table walk to obtain the physical address of the page table entry, separating the access mechanism from the address translation mechanism and freeing up page table entries for actual use.
Solution Approach 2:
The patent introduces an intermediary mechanism (the truncated page table walk performed by the MMU) between the software process and the page table entry. The MMU acts as a mediator that automatically retrieves the physical address of the page table entry without requiring the software process to perform recursive mapping, thus eliminating the need for dedicated recursive mapping entries.
2Ease of operation
If recursive mapping is used to access page table entries, then the page table entry can be accessed, but efficiency decreases due to cached mappings being usable only for subsequent recursive operations
Solution Approach 1:
The patent makes the page table walk mechanism universal by using the same truncated page table walk approach for both accessing page table entries and for address translation. The MMU's page table walker can be configured to perform either a full walk (for address translation) or a truncated walk (for page table entry access), eliminating the need for separate recursive mapping mechanisms and improving overall efficiency.
Solution Approach 2:
The patent changes the parameter of page table walk depth from fixed (always full depth for address translation) to variable (can be truncated to stop at intermediate levels). By controlling the number of levels traversed, the system can efficiently access page table entries without performing unnecessary full traversals, improving performance for page table maintenance operations.
Data Source
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Figure 3A~3C
AI summary
Optimizing access to page table entries in processor-based devices is disclosed. In this regard, an instruction decode stage of an execution pipeline of a processor-based device receives a memory access instruction including a virtual memory address. A page table walker circuit of the processor-based device determines, based on the memory access instruction, a number T of page table walk levels to traverse, where Tis greater than zero (0) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address. The page table walker next performs a page table walk of T page table walk levels of the multilevel page table, and identifies a physical memory address corresponding to a page table entry of the Tth page table walk level. The processor-based device then performs a memory access operation indicated by the memory access instruction using the physical memory address.