Hardware Page Table Walker with Region-Based Prefetching
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Solution Overview
Problem
The performance of translation lookaside buffers (TLBs) is hindered by high TLB miss penalties, especially in Big Data workloads with irregular memory access patterns, leading to slower performance and increased energy consumption due to the need for memory page-table walks.
Innovation Solution
A hardware page table walker predicts and prefetches page table entries using virtual memory region tracking information, breaking the serial page table walk procedure into parallel operations to reduce latency and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a hardware page table walker performs sequential memory page-table walks to retrieve physical addresses, then translation accuracy is maintained, but translation time increases and performance deteriorates
Solution Approach 1:
The patent applies preliminary action by predicting the physical address of the final page table entry (PTE) before the sequential page table walk completes. The prediction is performed using virtual memory region tracking information that captures the relationship between virtual base addresses and physical PTE addresses. This allows the system to prefetch the predicted PTE address in parallel with the ongoing page table walk, so that when the walk completes, the translation is already available or nearly available, significantly reducing translation time while maintaining accuracy through verification against the actual page table walk result.
Solution Approach 2:
The patent introduces a new dimension of parallelism by operating in two concurrent dimensions: the traditional sequential page table walk dimension and the prediction dimension. The prediction mechanism operates independently using virtual memory region tracking, creating a parallel pathway that does not interfere with the accuracy-guaranteeing sequential walk. This dimensional separation allows the system to pursue speed through prediction while preserving accuracy through the original sequential verification path.
2Measurement precision
If memory page-table walks are performed to resolve TLB misses, then correct physical address translation is achieved, but energy consumption increases
Solution Approach 1:
The patent reduces energy consumption by performing preliminary prediction of the final PTE address using virtual memory region tracking information. This prediction allows the system to prepare the translation result in advance, potentially avoiding or shortening the energy-intensive sequential page table walk through memory. The prediction mechanism uses cached virtual memory region data rather than performing additional memory accesses, thereby reducing the energy required to resolve TLB misses while maintaining translation accuracy through verification.
3Reliability
If page table walk operations are performed sequentially, then translation correctness is ensured, but productivity decreases due to serial dependency
Solution Approach 1:
The patent improves productivity by performing preliminary prediction of the final PTE address in parallel with the page table walk operations. The virtual memory region tracking information is updated and used to predict subsequent PTE addresses before the current page table walk completes. This breaks the serial dependency chain by allowing prediction and preparation to occur concurrently with verification, thereby increasing translation throughput while maintaining correctness through the verification process.
Solution Approach 2:
The patent introduces parallelism by creating a second dimension of operation that runs concurrently with the traditional sequential page table walk. The prediction mechanism operates in this new dimension using virtual memory region tracking, allowing multiple translation operations to be prepared in parallel rather than strictly sequentially. This dimensional addition increases translation throughput while the original sequential walk dimension continues to ensure correctness.
Data Source
AI summary
Methods and apparatus provide virtual to physical address translations and a hardware page table walker with region based page table prefetch operation that produces virtual memory region tracking information that includes at least: data representing a virtual base address of a virtual memory region and a physical address of a first page table entry (PTE) corresponding to a virtual page within the virtual memory region. The hardware page table walker, in response to the TLB miss indication, prefetches a physical address of a second page table entry, that provides a final physical address for the missed TLB entry, using the virtual memory region tracking information. In some implementations, the prefetching of the physical PTE address is done in parallel with earlier levels of a page walk operations.