Page Table Walker Detects Redundant Walks
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Solution Overview
Problem
Current processors face inefficiencies in managing page table walks, leading to redundant operations that consume unnecessary power and resources, particularly in systems-on-chip (SoCs) where multiple applications are executed simultaneously, due to the lack of effective redundancy detection mechanisms.
Innovation Solution
Incorporating a page table walk cache and a page table walker that compares matching levels with walk cache hit levels to detect and avoid redundant page table walks, thereby optimizing resource usage and reducing power consumption by skipping unnecessary memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor performs page table walks for every virtual address translation, then address translation accuracy is maintained, but power consumption increases and processing efficiency decreases due to redundant operations
Solution Approach 1:
The patent performs page table walks in advance for virtual addresses that are likely to be accessed soon, storing the results in a cache. When a virtual address is accessed, the translation result can be retrieved from the cache without performing a full page table walk, thereby avoiding redundant operations and reducing power consumption while maintaining translation accuracy.
Solution Approach 2:
The patent introduces a page table walk cache that stores translation results for specific virtual addresses. Instead of uniformly performing page table walks for all address translations, the system selectively retrieves cached results when applicable, creating a localized optimization that reduces redundant operations for frequently accessed addresses while maintaining full translation capability when needed.
2Measurement precision
If the processor performs complete page table walks for all virtual addresses, then translation accuracy is ensured, but processing time increases due to redundant memory accesses
Solution Approach 1:
The system performs page table walks in advance and caches the translation results. When a virtual address translation is needed, the system first checks the cache for an existing valid translation. If found, the cached result is used immediately, avoiding the time-consuming complete page table walk while ensuring translation accuracy through proper cache validation.
Solution Approach 2:
The patent creates a cached copy of page table translation results in a dedicated cache structure. This copy allows the system to retrieve translation information quickly without repeatedly accessing the full page tables in memory, significantly reducing processing time while maintaining translation accuracy through validation mechanisms.
3Adaptability or versatility
If the processor executes multiple application programs simultaneously, then system versatility is improved, but resource contention increases leading to more redundant page table walks
Solution Approach 1:
The page table walk cache is designed to handle translations for multiple application programs simultaneously. The cache stores translation results with associated validity information that allows the system to determine whether cached translations are applicable to current access requests from any application, providing a universal solution that reduces redundant operations across diverse workloads.
Solution Approach 2:
The system implements feedback mechanisms that track translation results and their validity status. When page table walks are performed for different applications, the results are fed back into the cache with appropriate validity markers. This feedback allows subsequent translation requests to efficiently determine whether cached results can be reused, reducing redundant operations while managing multi-application complexity.
Data Source
AI summary
A processor includes a page table walk cache that stores address translation information, and a page table walker. The page table walker fetches first output addresses indicated by first indexes of a first input address by looking up the address translation information and at least a part of page tables, and compares a matching level between second indexes of a second input address and the first indexes of the first input address with a walk cache hit level obtained by looking up the page table walk cache using the second indexes.