Paillier Decryption System Parallel Processing
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Solution Overview
Problem
Existing systems fail to efficiently handle arithmetic operations involving large integer bit widths required by the Paillier algorithm, leading to performance issues and high energy consumption.
Innovation Solution
A Paillier decryption system and method that divides the decryption process into subitems corresponding to prime numbers, reducing operational bit width and enabling parallel processing to improve computation speed and reduce energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Paillier algorithm is used for homomorphic encryption, then data security and user privacy are protected, but computation performance deteriorates and energy consumption increases due to large integer bit width operations
Solution Approach 1:
The patent applies segmentation by dividing the decryption process into multiple subitems corresponding to different prime numbers. The Paillier decryption operation with large integer bit width is segmented into parallel sub-operations with smaller bit widths, allowing independent processing of each subitem while maintaining the security properties of the original algorithm.
Solution Approach 2:
The patent transforms the single-dimension large integer operation into a multi-dimensional parallel processing structure. By introducing the dimension of parallel subitems corresponding to different prime factors, the system achieves computation speedup while maintaining the cryptographic security requirements of the Paillier algorithm.
2Reliability
If Paillier algorithm is used for homomorphic encryption, then data security and user privacy are protected, but energy consumption increases due to complex arithmetic operations with large integer bit widths
Solution Approach 1:
The patent segments the energy-consuming large integer operations into smaller suboperations corresponding to different prime numbers. Each subitem requires less computational energy, and the parallel execution of these subitems reduces the total energy consumption compared to sequential processing of the original large integer operation.
Solution Approach 2:
The patent performs partial actions on smaller prime number components rather than the complete large integer operation. By processing each prime factor separately and combining results, the system achieves the decryption function with reduced energy expenditure on each individual computational step.
3Adaptability or versatility
If existing CPU or GPU is used for Paillier decryption, then general-purpose computing is available, but computation speed is insufficient for large integer bit width operations
Solution Approach 1:
The patent segments the computationally intensive Paillier decryption into parallel subitems that can be efficiently processed by existing CPU or GPU architectures. The segmentation aligns with the parallel processing capabilities of these devices, allowing each core or streaming processor to handle a subitem independently, thereby achieving higher overall computation speed.
Solution Approach 2:
The patent introduces parallel processing dimension to exploit the multi-core architecture of modern CPUs and GPUs. By mapping each subitem to a separate processing unit, the system transforms a sequential bottleneck into a parallel computation problem that leverages the full computing power of available hardware resources.
Data Source
AI summary
A Paillier decryption system, IC, and method. The IC includes: a modular exponentiation module, for performing modular exponentiation operations related to a first subitem and a second subitem, where a Paillier decryption process of encrypted data is divided into a first subitem and a second subitem according to the Chinese remainder theorem, the first subitem corresponding to a first prime, the second subitem corresponding to a second prime, a public key of the encrypted data being a product of the first prime and the second prime, a bit width of the first prime being the same as a bit width of the second prime; a first module combination corresponding to the first subitem, for determining a computation result of the first subitem; and a second module combination corresponding to the second subitem, for determining a computation result of the second subitem.


