Pair Bit Line Programming for NAND Boost Voltage Clamping
Solution Overview
Problem
Program disturb in non-volatile memory devices, specifically due to insufficient boosting voltage that leads to unintended programming of unselected storage elements, remains a challenge, particularly as NAND technology scales down, resulting in boosting saturation or clamped voltages that fail to prevent program disturb.
Innovation Solution
A method involving alternating programming sequences with dual programming pulses and interleaved verify operations for pairs of bit lines, ensuring that at least one neighbor bit line is inhibited during each pulse, thereby increasing the boosting potential and preventing clamped voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pass voltages are applied to unselected word lines to boost the voltage of the channel area of unselected bit lines, then program disturb is reduced, but the boosting voltage becomes clamped or saturated at unacceptably low voltages
Solution Approach 1:
The patent segments the bit lines into different groups (first group and second group) and applies programming operations alternately to each group. By inhibiting one group while programming the other, the patent ensures that unselected bit lines have inhibited neighbors, which prevents junction leakage and maintains higher boosting voltages. This segmentation approach resolves the contradiction by organizing bit lines into manageable groups that can be controlled independently.
Solution Approach 2:
The patent applies preliminary inhibition to one group of bit lines before programming the other group. By pre-inhibiting the unselected bit lines and their neighbors, the patent prevents the junction leakage that would otherwise clamp the boosting voltage. This preliminary anti-action ensures that when programming voltages are applied, the boosting voltage remains high enough to prevent program disturb in subsequent operations.
2Reliability
If boosting voltage is increased to prevent program disturb, then unselected storage elements are protected from inadvertent programming, but the voltage becomes clamped due to junction leakage in scaled-down structures
Solution Approach 1:
The patent divides bit lines into segmented groups and applies alternating programming and inhibition patterns. This segmentation ensures that every unselected bit line has at least one inhibited neighbor, creating a protective barrier that prevents junction leakage. The segmented approach allows the boosting voltage to remain high without being clamped by leakage currents, thus protecting unselected storage elements while maintaining voltage levels.
Solution Approach 2:
The patent introduces inhibited bit lines as intermediary elements between programmed bit lines and unselected storage elements. These intermediary inhibited lines act as buffers that block the propagation of leakage currents and electric fields that would otherwise cause program disturb. By placing these intermediary inhibited lines adjacent to unselected storage elements, the patent effectively shields them from harmful effects while maintaining high boosting voltages.
Data Source
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AI summary
A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.