4n+1 Capacitive DAC Architecture With Paired-Capacitor Linearity
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Solution Overview
Problem
Sigma delta modulators require high-linearity digital-to-analog converters (DACs) for accurate analog-to-digital conversion, but achieving this with multi-level DACs is challenging due to the need for multiple capacitors and dynamic element matching, especially in switched capacitor designs where inaccuracies are directly transmitted to the signal.
Innovation Solution
A digital-to-analog converter of the charge transfer type with a capacitor switch unit capable of generating 4n+1 output levels, using a plurality of switching units to couple reference capacitor pairs with either a positive or negative reference signal, and a switching controller to control switching configurations for even and odd transfers to maintain linearity, employing a switched capacitor stage and reference voltage switching arrangements to generate switching patterns for each output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-level DACs are used to achieve high resolution and reduced quantization noise, then the accuracy and performance of sigma delta converters are improved, but the device complexity increases due to the need for multiple capacitors and dynamic element matching
Solution Approach 1:
The multi-level DAC is segmented into multiple two-level DACs operating in parallel, each handling a portion of the digital input words. This segmentation allows each sub-DAC to maintain simplicity with minimal capacitors and switches, while the combined output achieves the desired multi-level resolution. The segmentation principle resolves the contradiction by distributing the complexity across multiple simple units rather than requiring one complex multi-level DAC.
Solution Approach 2:
Multiple two-level DAC outputs are merged through a summing amplifier to produce the final multi-level analog output. This merging approach combines the simple, linear outputs of individual two-level DACs to achieve the complexity of a multi-level DAC, thereby improving conversion accuracy without requiring each individual DAC to be complex.
2Device complexity
If the number of capacitors and switches is reduced in multi-level DACs, then the device size and power consumption are reduced, but achieving high linearity becomes more difficult
Solution Approach 1:
Instead of building a complex multi-level DAC directly, the invention inverts the approach by using multiple simple two-level DACs and combining their outputs. This inversion allows the system to achieve multi-level linearity through the combination of inherently linear two-level converters, rather than attempting to achieve linearity in a single complex multi-level structure.
Solution Approach 2:
The parallel two-level DAC architecture provides inherent feedback mechanisms where each simple DAC contributes to the overall linearity. The summing of multiple linear two-level outputs creates a self-correcting system that maintains high linearity accuracy without requiring complex matching of numerous capacitors and switches in a single multi-level structure.
3Reliability
If dynamic element matching is implemented in multi-level DACs, then linearity is improved, but the manufacturing precision requirements and device complexity increase
Solution Approach 1:
The DAC is segmented into multiple independent two-level units, each with its own simple capacitor and switch configuration. This segmentation reduces the manufacturing precision requirements for each individual unit, as two-level DACs require less precise matching than multi-level DACs. The overall linearity is achieved through the combination of these segmented units rather than through precise matching of a large number of elements in a single structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more accurate sigma delta devices with minimal dynamic element matching and a reduced number of switches, maintaining linearity and achieving higher resolution with the same size and power as existing devices, while simplifying the matching of capacitors in multi-level DACs.
Implementation Method 1
capacitive charge transfer DACs are often used to realize the feedback of the modulator
Implementation Method 2
each output level is defined by a different amount of electrical charge transferred to the output of the DAC
Data Source
Figure 1~4
Figure 2
Figure 3a~3c
AI summary
A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+l output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.